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ECE 4110–5110 Digital System Design

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Presentation on theme: "ECE 4110–5110 Digital System Design"— Presentation transcript:

1 ECE 4110–5110 Digital System Design
Lecture #16 Agenda Test 1 Review Announcements Next: Exam #1 Closed Book Lecture #16 Page 1

2 Exam Review PLD Topics:
-PLA’s: Structure, Logic using compact representation -PAL’s/GAL’s: Structure components, Logic using compact representation, draw custom function blocks, distinguishing features, , advantages, disadvantages, configuration programming. -CPLD’s: Structure components, function block elements, realize logic functions using function blocks, distinguishing features, , advantages, disadvantages, configuration programming FPGA's: Xilinx/Altera families, function block elements, realize logic functions using function blocks, distinguishing features, configuration programming, advantages, disadvantages, configuration programming. Lecture #16 Page 2

3 Exam Review VHDL Topics: Design Abstraction Constructs (entity, architecture, packages) Ports/Signals (Internal/External, modes, types) Data Types (built-in, added using packages) Operators (built-in, added using packages) Structural Design (component declaration, instantiating, port maps, generate) Concurrent Assignments Simple Signal Assignment Conditional Signal Assignment Selected Signal Assignment Generics & Constants Behavioral Design (process execution, synthesis) Process (sensitivity lists, wait statements) Variables (:= vs <=) Sequential Assignments Simple If/Then/Elsif/Else Case Loops (simple, while, for) Attributes (event, transaction, last_value, last_event) Test Benches (Structure, reporting) - Decoders: Structural, Behavioral, Enables Lecture #16 Page 3

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