1. Adaptive Computing Systems
Instructor
Arun K. Somani
Tel:
Office Hours: MWF 10:00-11:00
Teaching Assistan : I will assist myself with your help
Web Page: Follow link from home page of department
Text Book: Only references and paper
Grading
Homework: Once every two weeks and reading, 25% of grade
Notes Scribing: You are responsible for two lectures, 25% of grade
Project: In the past, projects were mostly not as successful, but will try again to make it more successful experience, 50% of grades

2. Outline of the Course
Introduction to Adaptive/Reconfigurable Computing
FPGA Technology and Architectures
Spatial Computing Architectures
Adaptive Network Architectures
Reconfigurable Computing Architectures
Specialized computing

3. Introduction Rapidly changing field:
vacuum tube -> transistor -> IC -> VLSI
memory capacity and processor speed is doubling every 1.5 years:
So why we need reconfigurable computing?
Well, we always had it
Today’s computer are one of the forms of reconfigurable computers
Each user sees it mostly fit to do their computation
Specialized processors can not keep up with technology due to volume (mass production) of commercial processors
However, cheap reconfigurable computing can still compete with commercial processor in cost/performance ratio
FPGA make such implementations feasible

4. General Purpose Computing
Reconfiguration/Customization can occur at many levels
Market level
Market for device
System level
Running different pieces of code at different times
Application level
Same resources used by different instructions rather than building various different functional units
Algorithm level
Different algorithms can be used to realize the same application

5. Consider Reconfiguration
Here is a function: AX2 + BX + C
It can be viewed as steps of many binary operations
X*X, B*X, A*(X*X), (B*X)+C, (A*(X*X))+ ((B*X)+C)
Takes three time steps using three mult and two add FU
A*X, (A*X)+B, (A*X+B)*X, ((A*X+B)*X)+C
Takes four time steps using two mult and two add FU
A*X+B, (A*X+B)*X+C
Takes tow multiply-add time steps using one mult-add FU and two muxex
But what if we have a unit that can be configured as mult or add
mux (X, B, C), mux (A, res) and reconfigurable unit

6. Design a system We may like to design systems with flexibility
We also like to minimize amount of hardware
3 bit input, 24 bit output (like a controller for RISC processor)
4 bit input, one of any of 64K functions
12 bit input, 16 bit output, but only 16 unique combinations