1. COMP541 Sequential Logic – 2: Finite State Machines
Montek Singh
Sep 28, 2016

2. Buttons and Debouncing
Lab 6 Preview
Buttons and Debouncing

3. Lab Preview: Buttons and Debouncing
Mechanical switches “bounce”
vibrations cause them to go to 1 and 0 a number of times
called “chatter”
hundreds of times!
We want to do 2 things:
“Debounce”: Any ideas?
Synchronize with clock
i.e., only need to look at it at the next +ve edge of clock
Think about (for Lab):
What does it mean to “press the button”? Think carefully!!
What if button is held down for a long time?

4. Today’s Topics State Machines
How to design machines that go through a sequence of events
“sequential machines”
Basically: Close the feedback loop in this picture:

5. What is sequential logic?
Anything that is not combinational
has a cycle of gates
output cannot be determined solely by the current inputs
i.e., has state
But: Not all sequential circuits are useful
e.g., 3-inverter loop
is sequential because of feedback
but not controllable by a clock
Synchronous sequential logic: a useful form
follows a specific template

6. Synchronous Sequential Logic
Flip-flops/registers contain the system’s state
state changes only at clock edge
so system is synchronized to the clock
all flip-flops receive the same clock signal (important!)
every cyclic path must contain a flip-flop

7. Synchronous Sequential Logic
Flip-flops/registers contain the system’s state
state changes only at clock edge
so system is synchronized to the clock
all flip-flops receive the same clock signal (important!)
every cyclic path must contain a flip-flop

8. Examples
Some of these are synchronous sequential circuits, but some are not! Which ones?

9. Two common types Two common types of synchronous sequential circuits:
Finite State Machines (FSMs)
Pipelines

10. Finite State Machine (FSM)
Consists of:
State register that
holds the current state
updates it to the “next state” at clock edge
Combinational logic (CL) that
computes the next state
using current state and inputs
computes the outputs
using current state (and maybe inputs)

11. More and Mealy FSMs
Two types of finite state machines differ in the output logic:
Moore FSM:
outputs depend only on the current state
Mealy FSM:
outputs depend on the current state and the inputs
can convert from one form to the other
Mealy is more general, more expressive
In Both:
Next state is determined by current state and inputs

12. Moore and Mealy FSMs

13. FSM Example 1

14. Traffic Light Controller
Traffic sensors: TA, TB (TRUE when there’s traffic)
Lights: LA, LB

15. FSM Black Box
Inputs:
CLK, Reset, TA, TB
Outputs: LA, LB

16. FSM Specification When reset, LA is green and LB is red
As long as traffic on Academic (TA high), keep LA green
When TA goes low, sequence to traffic on Bravado
Follow same algorithm for Bravado
Let’s say clock period is 5 sec (time for yellow light)

17. States What sequence do the traffic lights follow?
Reset  State 0, LA is green and LB is red
Next (on board)?

18. State Transition Diagram
Moore FSM:
outputs labeled in each state
states: circles
transitions: arcs

19. State Transition Table
state graph encoded into a tabular format

20. “Encoded” State Transition Table
Symbolic states assigned bit codes
codes can be arbitrarily chosen
some are better than others (“optimal state coding”)

21. After Input and Output Encoding
Inputs and outputs assigned bit codes
again, codes can be arbitrarily chosen
again, some are better than others

22. FSM Schematic: State Register

23. Next State Logic
The truth table can be implemented and simplified using K-Maps:

24. Output Logic

25. FSM Timing Diagram: Study carefully!

26. Design Procedure Step-by-step procedure: Or, write Verilog and compile
given FSM description: codify it into a state diagram or table
assign codes to the states, inputs and outputs
derive Boolean equations and implement
Or, write Verilog and compile
the compiler follows the above steps
uses algorithms for optimal coding of states/inputs/outputs
uses algorithms for optimal Boolean implementation

27. FSM Example 2

28. A Sequence Recognizer Circuit has input, X, and output, Z
Recognizes sequence 1101 on X
Specifically:
if X has been 110 and next bit is 1, make Z high

29. How to Design States States remember past history
Clearly must remember we have seen 110 when next 1 comes along
Tell me one necessary state for this example…?

30. Beginning State Start state: let’s call it A
if 1 appears on input, move to next state B
output remains at 0
Input / Output

31. Second 1
New state, C
To reach C, must have seen 11

32. Next a 0 If 110 has been received, go to D
Next 1 will generate a 1 on output Z

33. What else? What happens to arrow on right?
Must go to some state. Where?

34. What Sequence? Here we have to interpret the problem statement
We have just seen 01
Is this beginning of new 1101?
Or do we need to start over w/ another 1?
Let us say that it is the beginning of a new run…

35. Cover every possibility
Must cover every possibility out of every state
For every state: X = 0 or 1
You fill in all the cases

36. Fill in

37. Full Answer

38. State Minimization Do we need all those states?
Some may be redundant
How to use as few states as possible?
State minimization is a well-studied problem
Is a tough problem (NP-complete)
but pretty good algorithms exist
exact and approximate
Out of the scope of this course

39. FSM implementation Do yourself: State transition table State encoding
Truth tables
Boolean equations and gate-level implementation

40. Reading
Read entire 3.3 and 3.4