1. Dept. of Info. & Comm. Eng. Prof. Jongbok Lee
Ch 10. Counter
Dept. of Info. & Comm. Eng.
Prof. Jongbok Lee

2. 1.Asynchronous Reset Counters
[1] Basic Synchronous Counter with asynchronous reset
entity cnt8 is
port (clk,reset : in std_logic;
q : inout std_logic_vector(7 downto 0));
end cnt8;
architecture behavioral of cnt8 is
begin
process(clk,reset,q)
if (reset=‘1’) then q <= “ ”;
elsif (clk’event and clk=‘1’) then q <= q + 1;
end if;
end process;
end behavioral;
vcom cnt8.vhd
vsim cnt8
view wave
add wave *
force clk 0 0ns,1 10ns -r 20ns
force reset 1
run 40ns
force reset 0
run 2000ns

4. [Counter for Emulation]
library unisim;
use unisim.vcomponents.all;
entity bin_counter is
port ( clk,reset : in std_logic:
q : inout std_logic_vector(3 downto 0));
end bin_counter;
architecture behaviroal of bin_counter is
component ibuf port (i:in std_logic; o:out std_logic); end component;
component bufg port (i:in std_logic; o:out std_logic); end component;
signal tmp,rclk : std_logic;
begin
u1 : ibuf port map (i=>clk,o=>tmp);
u2 : bufg port map (i=>tmp, o=>rclk);
process(rclk,reset,q)
if (reset=‘0’) then q<=“0000”;
elsif (rclk’event and rclk=‘1’) then q <= q + 1;
end if;
end process;
end behavioral;

5. Signal Pin No. Cable Connections clk H4 JP5.1 JP4.19 reset H3 JP5.2
q(0)
A12
JP7.1
JP2.41
q(1)
A14
JP7.2
JP2.42
q(2)
B14
JP7.3
JP2.43
q(3)
B13
JP7.4
JP2.44 G3 G4 H3 H4
P16 D9 C9
C12
B13
B14
A14
A12

6. #PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = “H4" ;
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "M14" ;
NET "q<0>" LOC = "A12" ;
NET "q<1>" LOC = "A14" ;
NET "q<2>" LOC = "B14" ;
NET "q<3>" LOC = "B13" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

7. 2. Asynchronous Counter Async. counter using decimal counter
Design a counter which counts from 0 to 9
If we use the output of above counter as the clock of next counter, 1/10 clock is generated, thus counter acts 10 times slower.
ex :
1MHz clock=>100KHz clock=>10KHz clock
advantage : simple
dis-advantage : slow

8. [1] basic decimal counter
entity count10 is
Port ( clk_in : in std_logic;
reset : in std_logic;
q : inout std_logic_vector(3 downto 0);
clk_out : out std_logic);
end count10;
architecture Behavioral of count10 is
begin
clk_out <= not q(3);
process(clk_in,q,reset)
if (reset='0') then q<="0000";
elsif (clk_in'event and clk_in='1') then
if (q = 9) then q <= “0000”;
else q <= q + 1;
end if;
end process;
end Behavioral;
vcom count10.vhd
vsim count10
view wave
add wave *
force clk_in 0 0ns,1 10ns -r 20ns
force reset 0
run 40ns
force reset 1
run 100ns

10. 3. Synchronous Counter synchronous counter
principle : use a shared clock for all the counters.
pros : fast
cons : complicated circuit
Frequency divider by M circuit using a synchronous counter : whenever counting from 0 to [M/2]-1, toggle the output clock, and then reset the counter.

11. [1] divide by 10 circuit
entity sync_counter is
port (reset : in std_logic;
clk : in std_logic;
clk_out : inout std_logic);
end sync_counter;
architecture behavioral of sync_counter is
signal count : integer range 0 to 4;
begin
process(reset, clk) begin
if (reset=‘0’) then count <= 0; clk_out <= ‘0’;
elsif (clk’event and clk=‘1’) then
if (count = 4) then
count <= 0; clk_out <= not clk_out;
else count <= count + 1;
end if;
end process; end behavioral;
vcom sync_counter.vhd
vsim sync_counter
view wave
add wave *
force clk 0 0ns,1 10ns -r 20ns
force reset 0
run 40ns
force reset 1
run 200ns

13. [3] Divide by 100 circuit
entity cnt100 is
port (reset : in std_logic;
clk : in std_logic;
clk_out : inout std_logic);
end cnt100;
architecture behavioral of cnt100 is
signal count : integer range 0 to 49;
begin
process(reset, clk) begin
if (reset=‘0’) then count <= 0; clk_out <= ‘0’;
elsif (clk’event and clk=‘1’) then
if (count = 49) then
count <= 0; clk_out <= not clk_out;
else count <= count + 1;
end if;
end process;
End behavioral;
vcom cnt100.vhd
vsim cnt100
view wave
add wave *
force clk 0 0ns,1 10ns -r 20ns
force reset 0
run 40ns
force reset 1
run 2000ns

15. % 실제 클럭을 입력보다 1억배 느린 클럭을 출력하는 동기회로