1. ALICE Trigger Upgrade CTP and LTU PRR
Introduction to Trigger Upgrade
David Evans
ALICE CTP and LTU Production Readiness Review
CERN 11th July 2017

2. This Morning’s Presentations
Introduction to Upgrade, trigger architecture, and prototype boards. David Evans
Summary and results of CTP/LTU board tests Marian Krivda
TTC-PON tests including full chain CTP-LTU-CRU tests Luis Alberto Perez Moreno
Pre-production plan David Evans

3. Summary of Upgrades MAPS Inner Tracking System (ITS)
Muon Forward Tracker (MFT)
MAPS Inner Tracking System (ITS)
Muon Arm Readout
Trigger electronics
(CTP + LTUs)
Data Acquisition (DAQ)
High Level Trigger (HLT)

4. CTP Requirements for Run 3
Interaction Rates: 50 kHz for Pb-Pb, and up to 200 kHz for p-p and p-Pb
2 modes of running for detectors: triggered and continuous
The main “interaction” trigger via the “FIT” detector
3 different latencies (LM, L0, L1)
All detector able to receive triggers, triggers can be sent every BC
For detectors using CRUs, CTP can act as throttle
For detectors not upgrading, BUSY signal still employed to stop triggers
Large latency means triggers will continue to be sent after BUSY set
No CTP Dead-time
3 types of trigger data distribution
Directly on detector (ITS and MFT detectors)
Via Common Readout Unit (CRU)
Via existing TTC system

5. Requirements for LHC Run 3 (cont.)
2 types of link layer (both optical)
TTC-PON (GBT) for upgraded detectors
Current TTC system for old detectors
14 detectors (9 with PON system, 4 with TTC system, TRD (TTC+PON))
6 Triggering detectors (FIT, ACO, EMC, PHO, TOF, ZDC; 34 inputs )
Trigger Input latencies (time from interaction to signal input at CTP)
425 ns (contributing detector – FIT)  Interaction (Minimum Bias) trigger
1.2 µs (contributing det. – ACO, EMC, PHO, TOF, ZDC)
6.1 µs (EMC, ZDC)
Note each detector sees only ONE trigger (LM, L0 or L1)
Except special cases (PHO and HMP)

6. Concept for New Trigger System
Keep the notion of the CTP
But advances in technology mean we can have CTP on a single 6U Board
Keep the notion of LTU
As the interface between CTP and detector/CRU
And as a standalone CTP emulator

7. ALICE System Block Diagram for LHC Run 3

8. Trigger Protocol Detectors with CRU: ITS/MFT TRD TTC detectors
One trigger over TTC-PON with different latencies
Payload: Event Id (32+12) bits, Trigger Type (32 bits)
ITS/MFT
One trigger over TTC-PON
One trigger over GBT
TRD
LM trigger to Front End over old TTC
TTC detectors
Protocol almost identical to Run2
For details see:

9. Trigger Types
Update: increased from 16 to 32 bits

10. LTU + TTCex boards (TTC drivers) LTU boards (GBT/PON drivers)
Design Proposal
1G Ethernet optical switch
IP bus
(Optical Ethernet)
TTC-PON splitter
LTU + TTCex boards (TTC drivers)
TTC
LM/L0 trigger
over copper cable
LTU boards (GBT/PON drivers)
…………………
TTC-PON splitter
Trigger PC in UX25-CRx
(IP bus sw)
TTC-PON splitter
10G PON
TTC-PON splitter
CTP
BUSY cables only for old detectors
PON/GBT/TTC optical links
Electrical connection
ALI-CRx
Cavern

11. Design
We are using the new Kintex-Ultrascale FPGA (XCKU040-1FFVA1156C)
Only available since latter part of 2015
The option to upgrade to an even more powerful Kintex-Ultrascale FPGA is included in the design
The design is based around a single universal trigger board (CPT/LTU board)
Having both CTP and LTU configurations
Interface between CTP and LTUs is via TTC-PON and optical fan-out units
Allows two-way data traffic between CTP and LTUs
CTP/LTU board will have a FMC mezzanine card and triple-width front panel (see later).
Will still be based on a VME-type 6U board (VME for power only)

12. CTP/LTU Board (3 VME slots)
USB-JTAG (programming of FPGA and SPI memory)
PM bus connector (voltage and temperature monitoring)
5 x LVDS LEMO (2x LM/L0 out, BUSY in, BUSY out, Fast LM in)
FMC board
LTU mode: FMC S-18 card (optional, GBT, Ethernet)
CTP mode: (70 LVDS I/O) – Trigger inputs etc.
8 x Lemo 00 B (BC in, ORBIT in, Scope A out, Scope B out, TTC-A out, TTC-B out, Pulser in, Spare in/out)
SFP+ for IP bus (it must be separate as SFP for RJ45 has wider end of SPF plug-in module )
2x6 SFP+ (GBT or TTC-PON)
(3 VME slots)
LEDs

13. FMC Card for CTP Config. For LTU mode:
Off-the-shelf FMC card with 8 SFP+ connectors (S-18 card)
For CTP mode:
New FMC card designed by colleagues in Kosice
70 LVDS inputs/outputs
i/o can be configured in blocks of 4 (using jumpers)

14. FMC Card Design

15. Portable Version of LTU
LTU board inside standalone box (ELMA Guardbox33 -> case 3)
Allows use of LTU in lab without need for VME crate and power supply.
Internal power supply + fan for cooling
Different version of front panel necessary (ELMA produce it).

16. ELMA Box Front Panel
Cooling vents

17. CTP/LTU Prototypes
Two prototype boards arrived at CERN on 7th March 2017
PCB files submitted to JALTEX on 2/12/16
One board had problem with regulator for 5V  sent back to JALTEK for repairs on 24/3/17
 returned 11/4/17

18. High-Density Board High density of components on front
And passive components on bottom side is impressive
Back

19. Board Testing Extensive testing of proto-type boards since early March
No major problems found
Only minor modifications to PCB required
See next talks

20. Summary
ALICE Trigger Upgrade keeps concept of a Central Trigger Processor (CTP) and Local Trigger Units (LTUs) for each sub-detector
Design centred around universal CTP/LTU board using the Xilinx Kintex-Ultrascale FPGA (XCKU040-1FFVA1156C).
Two prototype boards delivered to CERN on 7th March 2017
Extensive testing shows no major problems (see other talks).