1. LCFI Status Report: Sensors for the ILC
Konstantin Stefanov
CCLRC Rutherford Appleton Laboratory
ILC Vertex Detector Workshop, Ringberg 2006
Introduction
Sensor Development for the ILC
Column-Parallel CCDs
In-situ Storage Image Sensors
Summary and Plans

2. Introduction and Conceptual Design
337 ns
2820x
0.2 s
0.95 ms
Beam bunch structure at ILC
Multiple collisions
120 large sensors (e.g. CCDs) in 5 layers, 800 Mpixels (20 μm20 μm)
Main vertex detector parameters:
Excellent point resolution (3.5 μm), pixel size = 20 μm, close to IP
Low material budget ( ~ 0.1% X0 per layer), low power dissipation
Readout:
Avoids excessive event overlap, occupancy << 1%
Inner layer effectively read out at 50 μs intervals during the 1 ms pulse train (20 readouts) – information may leave the sensor or be stored in pixel
Outer layers read out at 250 μs intervals
Moderate radiation hardness: bulk damage from 61011 electrons/cm2/year and 109 neutrons/cm2/year, surface damage not expected to cause problems
Tolerates Electro-Magnetic Interference (EMI)

3. The Column Parallel CCD
Main detector work at LCFI
Every column has its own amplifier and ADC – requires readout chip
Readout time shortened by orders of magnitude
All of the image area clocked, complicated by the large gate capacitance
Optimised for low voltage clocks to reduce power dissipation
“Classic CCD”
Readout time  NM/fout N M
Column Parallel CCD
Readout time = N/fout

4. Hybrid assembly with Column-Parallel CCD (CPCCD) and CMOS ASIC
CPC1 Bump-bonded to CPR1
Hybrid assembly with Column-Parallel CCD (CPCCD) and CMOS ASIC
CPC1 : Two phase CCD, 400 (V)  750 (H) pixels, 20 μm square;
CMOS readout chip (CPR1) designed by the Microelectronics Group at RAL:
0.25 μm process
Charge and voltage amplifiers matching the outputs of CPC1
Correlated double sampling
5-bit flash ADCs and 132-deep FIFO per column
Everything on 20 μm pitch
Size : 6 mm  6.5 mm
Manufactured by IBM
Bump-bonded by VTT (Finland) using solder bumps
Bump-bonded CPC1/CPR1 in a test PCB

5. CPC1/CPR1 Performance
5.9 keV X-ray hits, 1 MHz column-parallel readout
Voltage outputs, non-inverting (negative signals)
Noise 60 e-
Charge outputs, inverting (positive signals)
Noise 100 e-
First time e2V CCDs have been bump-bonded
High quality bumps, but assembly yield only 30% : mechanical damage during compression suspected
Differential non-linearity in ADCs (100 mV full scale) : addressed in CPR2
Bump bonds on CPC1 under microscope

6. Next Generation CPCCD Readout Chip – CPR2
Voltage and charge amplifiers 125 channels each
Analogue test I/O
Digital test I/O
5-bit flash ADCs on 20 μm pitch
Cluster finding logic (22 kernel)
Sparse readout circuitry
FIFO
Bump bond pads
CPR1
CPR2
CPR2 designed for CPC2
Results from CPR1 taken into account
Numerous test features
Size : 6 mm  9.5 mm
0.25 μm CMOS process (IBM)
Manufactured and delivered February 2005
Wire/Bump bond pads
Steve Thomas, RAL

7. Tim Woolliscroft, Liverpool U
CPR2 Test Results
Test clusters in
Sparsified output
Parallel cluster finder with 22 kernel
Global threshold
Upon exceeding the threshold, 49 pixels around the cluster are flagged for readout
Tests on the cluster finder: works!
Several minor problems, but chip is usable
Design occupancy is 1%
Cluster separation studies:
Errors as the distance between the clusters decreases
Reveal dead time
Many of the findings have already been input into the CPR2A design
Tim Woolliscroft, Liverpool U
Tim Woolliscroft, Liverpool U

8. Next Generation CPCCD : CPC2
Clock bus
Main clock wire bonds
CPR1
CPR2
Temperature diode on CCD
Charge injection
Four 1-stage and 2-stage SF in adjacent columns
Four 2-stage SF in adjacent columns
Standard
Field-enhanced
No connections this side
Image area
Extra pads for clock monitoring and drive every 6.5 mm
Three different chip sizes with common design:
CPC2-70 : 92 mm  15 mm image area
CPC2-40 : 53 mm long
CPC2-10 : 13 mm long
Compatible with CPR1 and CPR2
Two charge transport sections
Choice of epitaxial layers for different depletion depth: 100 .cm (25 μm thick) and 1.5 k.cm (50 μm thick)
Baseline design allows few MHz operation for the largest size CPC2

9. CPC2 + ISIS1 Wafer ISIS1 5” wafers
One CPC2-70 : 105 mm  17 mm total chip size
Two CPC2-40 per wafer
6 CPC2-10 per wafer
14 In-situ Storage Image Sensors (ISIS1)
3 wafers delivered
CPC2-70
CPC2-40
CPC2-10

10. CPC2-40 in MB4.0 Transformer CPR1/CPR2 pads Clock monitor pads
Johan Fopma, Oxford U
Transformer drive for CPC2
“Busline-free” CCD: the whole image area serves as a distributed busline
50 MHz achievable with suitable driver in CPC2-10 and CPC2-40 (L1 device)
First clocking tests have been done

11. Transformer Drive for CPC2
Requirements: 2 Vpk-pk at 50 MHz over 40 nF (half CPC2-40);
Planar air core transformers on 10-layer PCB, 1 cm square
Operation from 1 MHz to > 70 MHz unloaded;
Parasitic inductance of bond wires is a major effect – fully simulated;
Work on the reduction of the CCD capacitance and clock voltage is continuing – range of test devices under development.
Brian Hawes, Oxford U
Transformer is bulky;
IC driver could be a better solution;
Design of the first CPCCD driver chip (CPD1) has started, goes for manufacture end of June
CPD1: 2-phase CMOS driver chip for 20 Amp current load at 25 MHz (L2-L5 CCDs)
0.35 μm process, size 38 mm2

12. First Data from CPC2
CPC2-10 (low speed version) works fine, here at 1 MHz clock
55Fe spectrum at -40 C and 500 ms integration time
Noise is a bit too high, external electronics is suspected
Devices with double level metal (busline-free for high speed) are being manufactured now

13. Radiation Damage Effects in CCDs: Simulations
Signal density of trapped electrons in 2D
Full 2D simulation based on ISE-TCAD developed
Trapped signal electrons can be counted
CPU-intensive and time consuming
Simpler analytical model also used, compares well with the full simulation
Window of low Charge Transfer Inefficiency (CTI) between -40 C and 0 C
This is very important for the viability of the CCD option and should be verified experimentally
Simulation at 50 MHz
Operating window
L. Dehimi, K. Bekhouche (Biskra U); G. Davies, C. Bowdery, A.Sopczak (Lancaster U)

14. In-situ Storage Image Sensor (ISIS)
Beam-related RF pickup is a concern for all sensors converting charge into voltage during the bunch train;
The In-situ Storage Image Sensor (ISIS) eliminates this source of EMI:
Charge collected under a photogate;
Charge is transferred to 20-pixel storage CCD in situ, 20 times during the 1 ms-long train;
Conversion to voltage and readout in the 200 ms-long quiet period after the train, RF pickup is avoided;
1 MHz column-parallel readout is sufficient;

15. In-situ Storage Image Sensor (ISIS)
Global Photogate and Transfer gate
ROW 1: CCD clocks
Additional ISIS advantages:
~100 times more radiation hard than CCDs – less charge transfers
Easier to drive because of the low clock frequency: 20 kHz during capture, 1 MHz during readout
ISIS combines CCDs, active pixel transistors and edge electronics in one device: specialised process
Development and design of ISIS is more ambitious goal than CPCCD
“Proof of principle” device (ISIS1) designed and manufactured by e2V Technologies
ROW 2: CCD clocks
On-chip switches
On-chip logic
ROW 3: CCD clocks
ROW 1: RSEL
Global RG, RD, OD
RG RD OD RSEL
Column transistor

16. The ISIS1 Cell
1616 array of ISIS cells with 5-pixel buried channel CCD storage register each;
Cell pitch 40 μm  160 μm, no edge logic (pure CCD process)
Chip size  6.5 mm  6.5 mm
Output and reset transistors
OG RG OD RSEL
Column transistor
OUT
Photogate aperture (8 μm square)
CCD (56.75 μm pixels)

17. Tests of ISIS1 Tests with 55Fe source
The top row and 2 side columns are not protected and collect diffusing charge
The bottom row is protected by the output circuitry
ISIS1 without p-well tested first and works OK
ISIS1 with p-well has very large transistor thresholds, permanently off

18. Visit us at http://hepwww.rl.ac.uk/lcfi/
Conclusion and Plans
CPCCD program well advanced:
Main work at LCFI
Hybrid assembly with CPCCD and CMOS chips works OK
Detector-sized chips CPC2 have arrived, first tests have been done
Started to develop the challenging CPCCD drive system
ISIS work will continue:
First ISIS prototype on CCD technology manufactured, first tests promising
Next-generation small pixel ISIS (CCD- or CMOS-based) will be actively pursued
Immediate plans:
Evaluate CPC2 and CPC2/CPR2 bump-bonded
High speed external drive to CPC2-40 as demonstrator for the L1 vertex detector
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