1. Recap: Lecture 1
What is asynchronous design? Why do we want to study it?
What is pipelining? How can it be used to design really fast hardware?

2. Homework Problem Alice and Bob live on opposite sides of a wide river:
Alice is supposed to send a message (say, a “Yes”/”No”) across to Bob around midnight. Both have flashlights, but neither owns a watch. What should they do? Suggest several strategies, and discuss pros and cons of each.

3. Solution 1 Alice uses 2 lamps: Bob uses 1 lamp:
1 to indicate that she is ready with the message, and
1 for the message itself
Bob uses 1 lamp:
to indicate that he has received the message
4 phases during communication:
got it
yes/no
Alice
ready
Bob

4. Solution 2 Alice uses 2 lamps: Bob uses 1 lamp:
Green lamp to indicate “yes”
Red lamp to indicate “no”
Bob uses 1 lamp:
to indicate that he has received the message
Also 4 phase communication:
got it no
yes
Alice
Bob

5. Solution 3 What if Alice and Bob could keep time?
Alice uses 1 lamp for the message:
At 12 midnight: turns on lamp if message = “yes”
At 12:01: turns lamp off
Bob needs no lamps!
Takes down the message between 12 and 12:01
Pros: Fewer signals, lesser processing needed
Cons: Alice and Bob must keep their clocks closely synchronized

6. Lecture 2: Asynchronous Datapaths
How is data represented in an asynchronous system?
How is information exchanged?

7. Data Representation Styles: Dual-Rail
Dual-rail: uses 2 wires per data bit
bit n
bit 1
bit m
Each Dual-Rail Pair: provides both data value and validity
provides robust data-dependent completion
needs completion detectors

8. Dual-Rail (contd.) OR together 2 rails per bit
Dual-Rail Completion Detector:
combines dual-rail signals
indicates when all bits are valid (or reset)
C-element:
if all inputs=1, output  1
if all inputs=0, output  0
else, maintain output value C
Done OR
bit0
bit1
bitn
OR together 2 rails per bit
Merge results using “C-element”

9. Data Representation Styles: Single-Rail
Single-rail “Bundled Datapath”: alternative approach
widely used
Features:
datapath: 1 wire per bit (e.g. standard sync blocks)
matched delay: produces delayed “done” signal
worst-case delay: longer than slowest path
done indicates
valid data
bit 1
request
bit n
bit m
done
matched
delay
function block
Practical style: can reuse sync components; small area
Fixed (worst-case) completion time

10. Handshaking Styles: 4-phase
4-Phase: requires 4 events per handshake
Request
Acknowledge
start
event
done
get ready for
next event
ready for
“Level-sensitive”  simpler logic implementation
Overhead of “return-to-zero” (RTZ or resetting)
extra events which do no useful computation

11. Handshaking Styles: 2-phase
2-Phase: requires 2 events per handshake
Request
Acknowledge
start
event
done
start next
next event
Elegant: no return-to-zero
Slower logic implementation:
logic primitives are inherently level-sensitive, not event-based (at least in CMOS)

12. Handshaking + Data Representation
Several combinations possible:
dual-rail 4-phase, single-rail 4-phase, dual-rail 2-phase, and single-rail 2-phase
Example: dual-rail 4-phase
bit m
bit 1
ack
dual-rail data: functions as an implicit “request”
4-phase cycle: between acknowledge and implicit request A B

13. Other Data Representation Styles
Level-Encoded Dual-Rail (LEDR)
2 wires per bit: “data” and “phase”
exactly one wire per bit changes value
if new value is different, “data” wire changes value
else “phase” wire change value
M-of-N Codes
N wires used for a data word
M wires (M <= N) change value
numbers used for N and M: have impact on…
information transmitted, power consumed and logic complexity
Knuth codes, Huffman codes, …
data
phase