1. Digital Design Lecture 9
Sequential Logic

2. A General Sequential Circuit

3. Synchronous Sequential Circuits

4. Set/Reset Latch (NORs)

5. Set/Reset Latch (NANDs)

6. SR Latch with Control

7. D Latch

8. Latch Symbols

9. Clock Response

10. Master-Slave D Flip-Flop

11. D-Type Positive-Edge Triggered Flip-Flop

12. Edge-Triggered D Flip-Flop Graphic Symbol

13. JK Flip-Flop

14. Flip-Flop Characteristic TablesD
0 1
Q(t+1)
0 - Reset Set
D – Flip-Flop T
0 1
Q(t+1)
Q(t) – No change Q(t) - Complement
T – Flip-Flop K J
Q(t+1)
Q(t) – No change – Reset – Set Q(t) – Complement
JK – Flip-Flop
Table 5.1

15. T Flip-Flop

16. D Flip-Flop with Reset

17. Sequential Circuit Analysis

18. State Diagrams

19. Sequential Circuit: D Flip-Flop

20. Sequential Circuit: JK Flip-Flop

21. State Diagram for JK Circuit

22. Sequential Circuit: T Flip-Flop

23. Mealy and Moore Models Finite State Machines
Output is a function of both the present state and the present input
See Figure 5-15 (Slide 16: Sequential Analysis)
Moore
Output is only a function of the current state
See Figure 5-18 (Slide 19: JK Flip-Flop)