1. Tilecal week (8 February 2012)
Status of upgrade work
in Clermont-Ferrand
Tilecal week (8 February 2012)
François Vazeille
Information on French supports
Mini-drawers
High Voltage system
Dividers
Very Front End and Front End electronics
Comments and summary
1/17

2. Information on French supports
…. knowing that without support: nothing is possible !
(The economic crisis is everywhere)
10 January 2012 (Paris): IN2P3 meeting on ATLAS upgrade
 Financial support to LPC to go on.
11 January 2012 (Clermont-Ferrand): CSP (Commission Suivi de Projet)
 Technical manpower at LPC to go on.
19 January 2012 (Clermont- Ferrand): LPC Scientific Council
(with external members)
 Conclusions not yet known but positive reactions,
important for us because we have a new Director.
June 2012 (Paris): IN2P3 Scientific Council
 Our Tilecal upgrade activities will be part of
a global Calorimetry approach.
The good progresses of our R&D works will play a major role.
2/17

3. Mini drawers: mechanics and services
Status: the concept has been validated
(see previous talk: Tilecal upgrade meeting 7 October 2011)
 Present activities: 2 activities in parallel
Short term works
Medium term works
Demonstrator:
adjustment of present
mini-drawers
Service holes for PMT blocks
Position index
Cooling
Drilling for Mother Boards and
other cards/services
Routing of services
Handling tool
R&D studies
on links and services
Handling procedure
Optimization of links and
services
Design of tooling
Design of mini-drawers
Request to Institutes:
Information on positioning of cards/services.
3/17

4. High Voltage system The 6 options will be reported in the next LoI:
no decision taken till now.
 Present activities
Short term works
Demonstrator:
adjustment of present
mini-drawers for 175
Services for HV distribution
(see previous slide)
HV source to find
Thought about the usefulness
of ″noise killers″
4/17

5. Dividers Status: the concept and the design have been validated
including the test bench.
 non-linearity <0.1%  Luminosity
with a safety factor > 10.
(see previous talk: Tilecal upgrade meeting 17 June 2011)
 Present activities
Short term works
Medium term works
Demonstrator:
20 bases made
30 bases soon available
Radiation tests
Before June 2012
- From Chicago: up to 45 Krad.
Next contact with Philippe Farthouat
about other tests.
5/17

6. Very Front End and Front End electronics
Status:
- The 2 first ASICs (FATALIC 1 and 2) have been validated.
- The choice of a ″current conveyor″ is well suited behind a PMT.
(many talks, the last one: Tilecal upgrade meeting 7 October 2011)
 Present activities: 2 activities in parallel
Very Front End
Front End
2 kinds of ASICs
FATLIC3 delivery: mid-March
New test card: in progress
Signal optimization from simulation
- Peaking time.
- Width.
New: TACTIC (12 bits ADC)
FATALIC 4 later
2 kinds of ASICs
First thought about MB2
Then 3in1 depending from the status of ASICs
More information
in next slides
6/17

7. VFE FATALIC3 contains the full chain but for the ADC
- Delivery by mid-March 2012.
- It will be tested using a new test card in progress (best current/linearity injection)
- It has already a rather large surface, so
the foundry cost being proportional to the area
 Decision to develop the ADC on a separated chip,
then to bond it on FATALIC3 for tests, before designing FATALIC4.
TACTIC (Twelve bits AdC for s-atlas Tilecal Integrated Circuit)
- IBM 130 nm technology (like FATALIC).
- 12bits 40MHz
- ″Pipeline ADC″  best resolution and speed.
- Present status: design of the amplifier in progress
(the most important block in this architecture, present at every stage).
- Order at the beginning of August.
Parallel study of a digital approach of the ″Integrator″
- Based on the numerical sum of converted signals at 40 MHz:
likely possible because of the very low noise in ASIC.
- First simulations in progress, then tests in building 175.
7/17

8. FE First thought about Mother Board 2
and its connections with 3in1 and Daughter Board.
8/17

9. - Intermediate steps before going to the optimum design:
 Amplifier for the analog output for trigger on the 3in1 card.
 Classical ADC on MB2 waiting for TACTIC chip.
 TACTIC bonded on FATALIC3, waiting for FATALIC4.
 Negative (discrete?) and positive (chip)? regulators.
 Connections of the Adders on MB2, etc.
Needed Low Voltages of the 3in1 card not yet defined:
 Very few if the ASIC is alone (1 positive only).
 One more for the DAC (negative).
 Additional ones in the hybrid solution
to supply the amplifier/shaping requested by the analog output for the trigger.
- The same exercise has to be made for the MB2 and the DB,
in order to supply the MB2 itself + Adders + DB.
Some information requested to Stockholm/Chicago on DB:
 Pinout and connectors between the MB and DB.
 Format of the data of ADC integrator and data for the DACs on DB.
 List of slow control signals decoded by the DB. …
9/17

10. Comments and summary
Towards the ″ideal″ scheme
Ideal scheme
10/17

11. A lot of advantages with respect to the present ATLAS scheme: ATLAS
PMT
PMT
A lot of advantages
with respect to the
present ATLAS scheme:
Minimum of cards, connectors,
cables
 less failures, easy handling.
- Lower power consumption.
Less sensitive to radiations.
Certification/tests easier.
Cheaper production.
- - HV
Base
Base
3in1
3in1
ADC
Pipe-line
Inte-
grator
Adders
Inter-
face
Inter-
face
Energy
Time
Energy
Time
Physics
calib.
Physics
calib.
Trigger
Trigger
ATLAS
Ideal
11/17

12. Interest of having an ASIC approach
From the LoI Phase I, page 43
(LAr context, but true for every part)
″The main benefit of such an approach w.r.t. a more traditional design based on discrete components relies on it being a cost effective solution which will remove challenging integration issues in the design and layout of printed boards as well as in its power management.″
12/17

13. Liquid Argon strategy with respect the trigger.
(From the meeting ″ATLAS France plans for upgrade″, 10 January 2012)
Saturation
New digital part for Phase-I
13/17

14. A first constraint Ideal Hybrid PMT PMT Base Base 3in1 3in1 Energy
Adders
Inter-
face
Inter-
face
Energy
Time
Energy
Time
Phys.
Calib.
Phys.
Calib.
Trigger
Trigger
Ideal
Hybrid
14/17

15. Hybrid PMT 2 other constraints: Amplifier in 3in1, ADC downstream,
while the ASIC will be able
to deliver directly
a digital information.
3in1
Base
ASIC
Ampli
3in1
Adders
Adders
Inter-
face
Inter-
face
Somewhere,
in order to mix to LAr
fully digital
on the detector
ADC
Energy
Time
Phys.
calib.
Trigger
Trigger
Hybrid
15/17

16. in addition to the natural steps that will go to the final ASIC:
- Waiting for the availability of TACTIC  Standard ADCs on MB2.
-TACTIC bonded on FATALIC3.
- FATALIC4,
with at a given time the suppression of the analog output.
It is not obvious that this “obstacle course”
is the best way to succeed !
16/17

17. Summary  R&D activities are well progressing,
but we should discuss why we focus only on PHASE-II,
while LAr should implement a digital trigger in Phase-I.
Information requested to Institutes about:
- The Daughter Board.
- The fixation holes of Mother Boards.
Some elements will be delivered to the 3 readout solutions:
- Active Dividers.
- First mini-drawers and tools.
- Rough approach of services (HV included).
Parallel study of mini-drawers and services.
Pre-tests of ASICs (FATALIC and TACTIC)
will be made in building 175,
independently from the true Demonstrator tests.
17/17