1. Assembly Language for Intel-Based Computers, 5th Edition
Kip Irvine
Chapter 2: IA-32 Processor Architecture
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2. Chapter Overview General Concepts IA-32 Processor Architecture
IA-32 Memory Management
Components of an IA-32 Microcomputer
Input-Output System

3. General Concepts Basic microcomputer design
Instruction execution cycle
Reading from memory
How programs run

4. MOS 6502 microprocessor in a dual in-line package, an extremely popular 8-bit design.
Die of an Intel 80486DX2 microprocessor (actual size: 12×6.75 mm) in its packaging.
Intel 80486DX2 microprocessor in a ceramic PGA package.
The die from an Intel 8742.

5. CPU, core memory, and external bus interface of a DEC PDP-8/I
CPU, core memory, and external bus interface of a DEC PDP-8/I. made of medium-scale integrated circuits

6. Basic Microcomputer Design
Clock synchronizes CPU operations
Control unit (CU) coordinates sequence of execution steps
ALU performs arithmetic and bitwise processing
Register is the high speed storage locations inside the CPU, designed to be accessed at much higher speed than conventional memory.
Memory storage unit is where instructions and data are held while a computer program is running
Bus is a group of parallel wires that transfer data from one part of computer to another. Consist three separate bus: data bus, control bus and address bus.

7. Clock synchronizes all CPU and BUS operations
machine (clock) cycle measures time of a single operation
clock is used to trigger events

8. What's Next General Concepts IA-32 Processor Architecture
IA-32 Memory Management
Components of an IA-32 Microcomputer
Input-Output System

9. Instruction Execution Cycle
Fetch - CU fetches I-1 and increment IP (instruction pointer or program counter)
Decode - CU decodes the I-1 function to determine what the instruction ill do. I-1 input operand passed to ALU, and signals sent to ALU indicating operation to be performed
Fetch operands- If instruction used input operand located in memory, CU use read operation to retrieve operand and copy to internal register.
Execute- ALU executes instruction I-1 using the named registers and internal register as operands and send the output to named registers and/or memory. ALU updates status flags
Store output operand-If the output operand is in memory, the CU unit use write operation to store the data.

11. Multi-Stage Pipeline-non-pipelined
Pipelining makes it possible for processor to execute instructions in parallel
Instruction execution divided into discrete stages
Example of a non-pipelined processor. Many wasted cycles.
Figure: 6-stage Non-pipelined Instruction execution

12. Pipelined Execution
More efficient use of cycles, greater throughput of instructions:
Enable overlapped execution of the instruction
Pipelined processor can process seven instructions in the same amount time of non-pipelined.
For k states and n instructions, the number of required cycles is:
k + (n – 1)
Figure: 6-stage pipelined execution

13. Wasted Cycles (pipelined)
When one of the stages requires two or more clock cycles, clock cycles are again wasted.
For k states and n instructions, the number of required cycles is:
k + (2n – 1)
Figure: Pipelined execution using a single pipelined

14. Superscalar
A superscalar processor has multiple execution pipelines. In the following, note that Stage S4 has left and right pipelines (u and v).
For k states and n instructions, the number of required cycles is:
k + n
Figure: Superscalar 6-stage pipelined processor

15. Reading from Memory
Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are:
Cycle 1 = address bits of memory placed on address bus
Cycle 2 = Read Line (RD) set low, notify memory to read value
Cycle 3 = CPU waits one cycle for memory to respond, memory controller places operand on the data bus
Cycle 4 = Read Line (RD) goes to 1, indicating that the data is on the data bus

16. Cache Memory
Computer use high speed cache memory to hold most recently used instruction and data
High-speed expensive static RAM both inside and outside the CPU.
Level-1 cache: inside the CPU
Level-2 cache: outside the CPU
Cache hit: when data to be read is already in cache memory
Cache miss: when data to be read is not in cache memory.

17. Types of cache memory IA-32 processor have 2 types Level 1
smaller, fastest, more expensive
Level 2
once outside the processor, is now integrated into the chip.

18. Why Cache?
Even the fastest hard disk has an access time of about 10 milliseconds
2Ghz CPU waiting 10 milliseconds wastes 20 million clock cycles!

19. Step-by-Step Use of Cache

20. Step-by-Step Use of Cache

21. Performance Advantages
Hit ratios of 90% common
50%+ improved execution speed
Locality of reference is why caching works

22. How a Program Runs

23. Multitasking OS can run multiple programs at the same time.
Multiple threads of execution within the same program.
Scheduler utility assigns a given amount of CPU time to each running program.
Rapid switching of tasks
gives illusion that all programs are running at once
the processor must support task switching.