1. Minimization and Sequential Logic
CS/COE 0447 (term 2181)
Jarrett Billingsley

2. Class announcements Things are better!!!
Project 2 will be out next week
Pushed it back a week anyway since it didn't make sense not to…
Here's your exams!!!!!!!
I will be calling out letters. Come up when the FIRST LETTER OF YOUR USERNAME is called.
Now let's talk about it!
10/24/2017
CS/COE 0447 term 2181

3. …as I was saying 2 weeks ago, Minimization
10/24/2017
CS/COE 0447 term 2181

4. Karnaugh Maps (K-maps) – Setting up
A Karnaugh Map is a tool for minimizing boolean functions.
Let's start with a function that has two inputs.
Truth Table
K-map
Write input values in Gray code along axes. (Here there's only one input on each axis, so it's just 0 1.)
Fill in cells from truth table. A B Q 1 1 𝐁 𝐀 1 1 1 1
10/24/2017
CS/COE 0447 term 2181

5. Karnaugh Maps (K-maps) – Finding rects
Find rectangles of 1s with power-of-two width and height. (1, 2, 4, 8…)
Overlapping is totally fine! It's good!
Use the biggest rectangles possible.
Use the fewest rectangles possible. 𝐁 𝐀 1
10/24/2017
CS/COE 0447 term 2181

6. Karnaugh Maps (K-maps) – Interpreting rects
For each rectangle, look at the values of the variables along the axes. Some variables change, and others don't.
Which variable changes in the red rectangle? Which doesn't?
What about the blue rectangle?
Each rectangle is an AND term.
Write the variables that stay the same for that rect (keeping the NOT bars).
OR all the terms together.
WHEW! 𝐁 𝐀 1
Red: 𝐁
Blue: 𝐀
𝐐=𝐀+ 𝐁
10/24/2017
CS/COE 0447 term 2181

7. One order for the carry-out bit
With more than 2 variables, put two along one axis (GRAY CODE!). Ci A B Co 1
Try to make the rectangles as big as possible. Overlap is goooood. 00 01 11 10
Red: 𝐀 𝐂 𝐢
𝐀 𝐁
𝐀 𝐁 𝐀𝐁
Green: 𝐀𝐁 𝐂𝐢 1
Blue: 𝐁 𝐂 𝐢 1
𝐂 𝐨 =𝐀 𝐂 𝐢 +𝐀𝐁+𝐁 𝐂 𝐢
10/24/2017
CS/COE 0447 term 2181

8. This is really a 2x2 rectangle. It's just… doing its best.
Just like a 2D RPG…
Rectangles on K-maps can wrap around the edges. 00 01 11 10
𝐗 𝐘
𝐗 𝐘 𝐗𝐘
Red: 𝐘
Blue: 𝐗 𝐙 𝐙 1
𝐐= 𝐘 + 𝐗 𝐙 1
This is really a 2x2 rectangle. It's just… doing its best.
10/24/2017
CS/COE 0447 term 2181

9. Okay, maybe it's not perfect.
Let's try the Sum output of a full adder.
A 1x1 rectangle becomes a term that uses all the variables. 00 01 11 10
𝐀 𝐁
𝐀 𝐁 𝐀𝐁
Red: 𝐀𝐁 𝐂 𝐢
Green: 𝐀 𝐁 𝐂 𝐢 𝐂𝐢 1
Blue: 𝐀𝐁 𝐂 𝐢 1
Purple: 𝐀 𝐁 𝐂 𝐢
𝐒𝐮𝐦= 𝐀𝐁 𝐂 𝐢 + 𝐀 𝐁 𝐂 𝐢 +𝐀𝐁 𝐂 𝐢 +𝐀 𝐁 𝐂 𝐢
But wait, didn't we say that we could do it as:
𝐒𝐮𝐦=𝐀⨁𝐁 ⨁𝐂 𝐢 (that's xor!)
10/24/2017
CS/COE 0447 term 2181

10. Tradeoffs, tradeoffs There are extensions to K-maps to detect XORs.
But…
XOR gates are slower than AND/OR gates.
If area is a concern, an XOR might make sense.
If speed is a concern, AND/OR gates make sense.
What do real hardware designers do?
they use programs to do this stuff for them lol
Things like FPGAs, CPLDs, and GALs are reconfigurable hardware which usually use "sum-of-products" to do logic, so ANDs and ORs are all you've got
10/24/2017
CS/COE 0447 term 2181

11. Sequential Logic
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CS/COE 0447 term 2181

12. Remember, remember…
In combinational logic, the outputs depend on the current inputs.
In sequential logic, the outputs depend on the current and previous inputs.
That is, sequential logic is able to remember things.
What's the smallest bit of information you can remember?
A…………….
bit.
10/24/2017
CS/COE 0447 term 2181

13. 𝐑 𝐐 𝐒 The SR Latch A B Q 1 𝐐= 𝐑+ (𝐒+ (𝐑+ (𝐒+ (𝐑+ (…
Here's a confusing circuit:
S stands for set (turn it to 1), and R for reset (turn it to 0).
What's the boolean formula for Q?
𝐐= 𝐑+ (𝐒+ (𝐑+ (𝐒+ (𝐑+ (…
?????????????????????
This doesn't make sense from a combinatorial view.
Let's build it in Logisim.
It… works?
Notice how it starts off in an error state. 𝐐 𝐑 𝐒
NOR A B Q 1
10/24/2017
CS/COE 0447 term 2181

14. Why does it work?
Because it takes time for electrical signals to move through the wires and through the gates. (What's that called again?)
NOR 𝐑 A B Q 1 𝐐
We say this circuit is bistable - it has two (bi) states where its output is stable or steady. It's like a light switch. 𝐒
10/24/2017
CS/COE 0447 term 2181

15. Which input went to 0 first?
But it can break…
If we input 1 for both R and S…
That's stable. But the problem is when we input 0 on both now.
NOR 𝐑 A B Q 1
Which input went to 0 first? 𝐐
If R went to 0 first, then Q = 1.
If S went to 0 first, then Q = 0. 𝐒
If they both went to 0 at the exact same time, it will oscillate (flip back and forth)!
10/24/2017
CS/COE 0447 term 2181

16. These are not great. It would be nice to avoid them.
A truth table in time
For sequential logic, the next state depends on the previous state.
So the previous state becomes another input!
Q is our remembered value.
How Q changes depends on its current value and the inputs.
Qnext says what Q will become. Q S R 1
Qnext 1 ?
These are not great. It would be nice to avoid them. 1 1 ?
10/24/2017
CS/COE 0447 term 2181

17. A better memory cell: the D Latch
If we stick some AND gates in front of the SR latch, we get a D(ata) latch.
Now we have enable and data inputs.
When the enable input is 0… nothing happens.
When the enable input is 1… it mirrors Data.
When the enable input goes from 1 to 0…
It remembers what the Data was! Q E D 1
Qnext 1 1 1 1
10/24/2017
CS/COE 0447 term 2181

18. Tick tock
Sequential logic is based on time, and time is continuous.
Trying to build sequential circuits without anything to keep track of time is… possible, but very very difficult.
This is why we use a clock signal: it goes 0, 1, 0, 1, 0, 1…
rising edge
falling edge 1
time
We can synchronize our circuits on a clock edge: when it changes between 0 and 1.
10/24/2017
CS/COE 0447 term 2181