1. Status of upgrade works at Clermont-Ferrand
EVO meeting July 27th 2012
François Vazeille
First conclusions from the CERN tests (week 29) of 2 new concepts:
- The ″Slider″ tool in the mini-drawer handling.
- The ″Digital integrator″ for the cesium calibration.
 Status of mechanics and electronics activities for the Demonstrator.
More details will be given at the next Tilecal week (September 28th) 1

2. MECHANICS  Mini-drawers
 The 4 mock-ups have been machined to fit the Demonstrator constraints:
locking of PMT Blocks, cooling, etc.
An additional machining could be required in order to leave more space
at the readout side  shape of the Slider (see next slide).
The main goals are to deliver this train to Chicago as a first Demonstrator,
then to trust their evolution to Bucarest once conclusions will be drawn
 production of 2 other trains of 4 mini-drawers
(for Argonne and Clermont-Ferrand). 2

3.  CERN test of the Slider in B 175
Drawer
NEW CONCEPT (alignment inside):
the tool is supported
in the rear part of Girder rings
Tests made on these 3 Modules 3

4. in the absence of Fingers (362 mm kept to simulate the Finger room)
Tests made
in the absence of Fingers
(362 mm kept to simulate
the Finger room)
Alignment on 2 Girder rings at left (1 at right)
from their internal parts.
Very easy insertion of mini-drawers.
True on the 3 Tilecal modules. 4

5. Conclusions The Slider concept is fully validated:
- recovery of the internal alignment using the external guiding of Girder rings,
- easy sliding of mini-drawers.
Next evolutions are foreseen
- To lengthen the Slider in order to use at least 3 Girder rings from both sides.
- In order to keep the stiffness from the Finger (and not from the Girder rings)
when the Basket (supporting the mini-drawer) will be connected
 To study a possible recovery fixation adjustment
Adjustable contacts
Finger
Basket
Slider
Adjustable contacts
To provide allowed envelops of readout space to the 3 Institutes,
in particular the allowed height.
- To design the Baskets. 5

6. ELECTRONICS  High Voltage part  Very Front End electronics
Active Dividers: second production foreseen to provide 3 Demonstrators,
but enough for the first one (Chicago).
HV bus cards: design ready, production soon.
HV regulation system outside drawers: well advanced.
Services: well advanced,
but tests are foreseen on a long HV multiconductor cable.
 Very Front End electronics
Tests of FATLIC3 on the Clermont test bench: completed (T. Edvard)
 summary at the next Tilecal week.
 TACTIC1 (12 bits ADC)  CERN order to the foundry these days. 6

7. CERN test of the digital integrator in B 175
Test using
the big D6 cell
with 2 rows of
75 Tiles
PMT # 38
Nominal HV D6
3in1: FATALIC3 +
14 bit commercial ADC 7

8. FPGA
ADC
40 MHz
Laptop on labview 8

9. - Sum of 4000 samples (40 MHZ samples)
 FPGA
- Sum of 4000 samples (40 MHZ samples)
 Data every 100 µs to the laptop.
- Offset adjustment (on the sums) from labview.
On-line calculations
(for a given adjustable time constant: 10 ms for example).
Off-line calculations for any time constant.
Many tests before the cesium motion:
noise levels in various conditions: temperature, HV on/of… 9

10. … whereas simulations foresaw 1 source event every 13 samples.
Then source motion
… whereas simulations foresaw 1 source event every 13 samples.
First question: did we see the source effect? YES !
Second question: did we see the usual ″comb″ shape? YES !
New tests after a stabilization night  detailed results.
NOTHING TO SHOW TODAY:
results on the computer of Dominique … who is away this week !
 All the results will be shown by September 28th. 10

11. Many thanks to Irakli and Oleg for their help !
Conclusions
The digital integrator concept is validated,
rather close to the simulations.
We have now a full knowledge of the absolute values of
signal and noise levels
 Comparison with standard spectra will be made (taken some days before).
Some improvements are expected!
- To have at CERN the next time the off-line analysis ready to be used.
- To decrease the noise level as much as possible
 Using the commercial ADC with its optimization of the 3in1 card.
 But especially thanks to the future integration
of TACTIC in FATALIC: the best association with respect to
the signal integrity and the noise level.
Many thanks to Irakli and Oleg for their help ! 11