1. Basics of Converter Technology
DATA ACQUISITION
Basics of Converter Technology
Function
Data Sheet Characterizations
Quantization Error and SNR
Gain, Offset Errors
Linearity Errors and THD
SINAD
Electronic Design

2. DATA ACQUISITION BASICS
ANALOG VOLTAGE RANGE
VFS
QUANTIZED INTO
2n LEVELS
WHERE n = # OF BITS
Nominal Quantization Step
Nominal Step Size Q = VFS/2n
Highest Voltage Step = VFS – Q
Max Count = 2n –1 (0 is a valid step)
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3. Ideal 3 Bit A/D Converter Transfer Function
Quantization Error
Note: Last step occurs at VFS(N-1)/N under ideal conditions
Voltage is Measured as Fraction of a reference Vref
VFS = Vref
Quantization Error
Ideal 3 Bit A/D Converter Transfer Function
Electronic Design

4. Max Quantization Error: Qerr = VFS/(2n) = 1 bit
A/D
D/A
Max Quantization Error:
Qerr = VFS/(2n) = 1 bit
Electronic Design

5. More Resolution may require, slower speed, higher power
SNR = 20 log(2(n-1) * sqrt(6) )
= 20log (2(n-1)) + 20log (sqrt(6))
= 20(n-1)log(2) + 20log (sqrt(6))
= 20nlog(2)-20log(2)+20log (sqrt(6))
= 20nlog(2) + 20log (sqrt(6)/2)
= 6.02n n
A/D
D/A
Sinewave MAX SNRDB = 6.02n
Max Quantization Error, Qerr = VFS/(2n) = 1 bit
More Resolution (higher n) means less quantization error
Examples:
VFS = 10V, n = 8 Bit, Qerr = 39.96mV, SNRmax = 49.9DB
VFS = 10V, n = 12Bit, Qerr = 2.44mV, SNRmax = 74.0DB
VFS = 10V, n = 16Bit, Qerr = 0.16mV, SNRmax = 98.1DB
More Resolution may require, slower speed, higher power
Electronic Design

6. Example of ½ Bit Offset Error
Offset Error: Shifts Ideal Staircase Function Right (+) or Left (-) by Max Voltage or Max LSBs
Electronic Design

7. Gain Error will change the converter “slope”
Gain Error: Changes Ideal Staircase Function so that last step is not at VFS(N-1)/N
Electronic Design

8. Integral Linearity Error: Max Deviation from Ideal Straight Line
(INL: Integral Non-Linearity)
Xfer Curve drawn at midpoint of each input step (ideal vs actual)
Electronic Design

9. Differential Linearity Error: Max Deviation from Ideal Step Size
(DNL: Differential Non-Linearity)
DNL max > 1 Bit can lead to missing codes
Electronic Design

10. Linearity Errors Induce Harmonic Distortions
D/A
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11. SINAD: Signal-to-Noise Ratio and Distortion
ENOB: Effective Number of Bits
Combination of SNR and THD specifications
Measure of overall “usable” Dynamic Performance
In Ideal Converter ENOB = n
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12. Power Supplies are Extremely Important !!
PSRR: Power Supply Rejection Ratio
Measure of output noise injected by PS noise
PSRR is function of frequency
Degrades with frequency
A/D converters require “quiet” supply voltages
Use adequate bypass capacitances
Isolate supply voltages using separate regulators
Electronic Design

13. A/D Converter Architectures
DATA ACQUISITION
A/D Converter Architectures
Flash High Speed, High Power
Integrating High Resolution, Parallel
Successive Approximating Low Resolution, High Speed
Electronic Design

14. Successive Approximating (SAR)
END OF CONV
SUCCESSIVE
APPROXIMATION
REGISTER
n-1
n-2
n-3
Decision signal n
OUTPUT
BITS
CONTROL
CLOCK
Clock
n-n
V Ref B
BIT
D/A
Converter
n-1
COMPARATOR
n-2
n-3
V in
Buffer
n-n
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15. Integrating 318-595 Electronic Design n Output Bits CLOCK Clk
COUNTER
n-1
n-2
n Output Bits
n-3
V in
Buffer
CLOCK
n-n
COMPARATOR
Clk
Clr
Current
Source
CONTROL I C
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16. FLASH 318-595 Electronic Design OUTPUT LOGIC REGISTER n Output Bits
V Ref
OUTPUT
LOGIC
REGISTER
n-1
n-2
n-1
n-2
n Output Bits
V in
BUFFER
n-3
n-n
2n –1 COMPARATORS 1
Electronic Design