1. CMOS RFIC Design for Direct Conversion Receivers
Zhaofeng ZHANG
ELEC, HKUST

2. Outline of Presentation
Background Introduction
Design Issues and Solutions
A Direct Conversion Pager Receiver
Conclusion

3. Research Goal SOC Low Cost Low Power Process: CMOS Integration level
Device is good enough
Improved passive components
Integration level
Minimize external components
Minimize IC area and pin numbers
Low Power
High integration = low power
Low power individual block design
System architecture is important
SOC

4. Heterodyne Receivers High IF: more than 2 down-conversions Low IF
Best sensitivity
Need off-chip image-rejection SAW filters and channel-selection filters
Highest cost, high power, low integration
Low IF
Relaxed image-rejection requirement compared to high-IF
No DC offset problem
Quadrature LO is required
Flicker noise may be a problem
High integration level, low cost

5. Homodyne Receivers Pros Cons I 90º Q Simple architecture
LNA
Pros
Cons
Simple architecture
No image problem
No 50ohm interfaces
High integration level
Lowest cost, low power
DC offsets
Flicker noise
LO leakage
Even-order distortion

6. Origin of Problem Our research focus!
DC offsets
Flicker noise
LO leakage
Even-order distortion
Linearity requirement
Noise requirement
IQ mismatch
All problems are limited by the mixer design!
The mixer: the most critical component!
Our research focus!

7. DC Offsets & LO Leakage LO Leakage Zero IF + Offset
The offset originates from self-mixing.
It can be as large as mV range at the mixer output.
It varies with the environment and moving speed of
the mobile and changes with time.
The maximum bandwidth can be as large as kHz range.
LO leakage forms an interference to other receivers.

8. Spectrum Illustration
Power
Narrow Band
Broad Band
Frequency
Signal
DC Offsets
Offset-Free
DC offset
High-pass corner
Flicker noise
Let’s see the effect of the offset on the demodulated signals. The left side is demodulated narrow band signals. The right side is demodulated broad band signals. They are contaminated by the flicker noise associated with CMOS devices. In addition to this, time-varying dc offset can not be avoided in the conventional mixers. The top two are with dc offset and the bottom two are without dc offset. To prevent from signal blocking, we must filter those garbage out and high pass the signal. The high pass corner depends on the maximum DC offset bandwidth. The signal energy near DC will be lost and it will lead to very bad BER performance. This is true especially for narrow band signals. For broad band signals, such as spread signals, only a small portion is filtered out and dc offset has less influence. But if we can solve the DC offset problem, the high pass corner can be as small as possible, only static DC offset induced by device mismatch is our concern. The BER performance can be improved a lot.

9. Existing Solutions on DC Offset
AC coupling or high pass filtering
Autozeroing or double sampling
Offset cancellation in digital domain
Double LO frequency method [ISSCC99]
Adaptive dual-loop algorithm combined with the mixer [RAWCON00]
Pulse-width-modulation based bipolar harmonic mixer [CICC97]
However, these methods are either not so effective or too complicated, or not suitable for CMOS process.
There were many efforts on the offset: autozeroing or double sampling, effectively high pass filtering. However, it only can be used at the very late stage due to noise aliasing induced high noise floor. Also it needs a clock. AC coupling can be used in those very broad band modulation and DC-free coding. Very large capacitors can not be avoided. The offset can be processed in DSP part. The condition is the dc offset is not large enough to saturate the circuits and only static dc offset can be cancelled. Double LO frequency method can help but not too much because substrate coupling is not so sensitive to the separation distance. Above four methods do not focus on the self-mixing source-mixer, therefore self-mixing problem can not be solved completely. Adaptive dual-loop algorithm use feed-back to control the mixer. It only can reduce very large time-varying offset. Pulse-width-modulation based harmonic mixer only can be used for bipolar devices. We proposed a kind of square-law based harmonic mixer suitable for CMOS circuits in RAWCON conference.

10. Proposed Harmonic Mixing
Conventional
Our Work
flo=frf
RF Signal
frf
BB Signal
2flo=frf
LO Leakage
DC Offset
flo=frf/2
flo
So, what is harmonic mixing? Unlike conventional mixer, LO signal and RF signal are not in the same frequency band. It is the second harmonic of LO signal conducts the mixing process. Any LO leakage will be mixed with the second harmonic and creates no DC offset.

11. Square-law Based Mixer
Vlo+
Vlo-
Vrf+
Vrf- 3V LO 2 RF IF
Current
Voltage
Coupling No
How to realize it? We proposed the square-law based harmonic mixer here. We convert the LO input to the current form which contains second harmonic of LO and use this current to control the transconductances of the RF stage. There is no coupling between the current and the RF input and therefore ideally self-mixing free. The right side is the mixer core circuit. The bottom is a frequency doubler. Here we use the current to control the transconductances of the mixer rather than the conventional voltage controlled switches. The current injection is used to reduce the current flowing in M3 and M4 and therefore reduces flicker noise. Since the transconductances change simultaneously, there is no noise contribution from LO stage and the current source.
LO leakage free.
Ideally self-mixing free.
Current controlled switching.
No noise contribution from LO stage.

12. Flicker Noise Reduction
Vlo+
Vlo-
Vrf- 3V
Vrf+
Flicker noise is proportional to the current.
Current injection is used to reduce flicker noise.
No noise contribution from current source too.

13. Offset Cancellation 20 TSMC0.35 10 >35dB Gain (dB) -10 -20 -30 -40
Gain (dB)
-10
-20
-30
-40
-22
-20
-18
-16
LO Input Power (dBm)

14. Noise Performance 60 50 Noise Figure @ 10kHz (dB) 40 30 20 400 600 800
1000
Injected Current I0 (A)

15. How to improve more?
However, flicker noise is still too large due to CMOS devices, minimum noise figure achieved is larger than 10kHz for CMOS harmonic mixer. It requires a high gain and low noise LNA to overcome flicker noise while the front-end linearity suffers.
For a narrow-band communication system such as FLEX pager, the noise requirement at low frequency is very tough.
It is well known that bipolar device is a good candidate to eliminate flicker noise.
But, can we do it in a CMOS process and how good is the device? YES!
DC offset problem has been solved successfully. However, as you see, the noise performance is still not good enough due to large flicker noise. So how to improve?
It is well known that flicker noise in bipolar device is very small. But we are using a CMOS process. So lateral bipolar in a CMOS may be a good candidate to eliminate flicker noise. We tried this.

16. Lateral Bipolar Transistor in a Bulk CMOS Process
W.T. Holman95
Gate
Emitter
Collector
Base
Ground P+ N+
Vertical
Lateral
Here is the layout topview of lateral bipolar transistor. Only PNP is available in a nwell CMOS process. Emitter inside, with poly gate isolating emitter and collector, the nwell is used as the base. The gate is used to shut down the PMOS transistor.

17. Physical Model of LBJT Gate D. Mac98 Base P-Sub
Emitter
Collector
Base M1 Q1 Q2 Q3
Pure LBJT: M1, Q3 off, Q1, Q2 on.
This is the physical model of the lateral bipolar. One mos device, one lateral pnp, and two parasitic vertical bipolars.

18. Gummel Plot of LBJT TSMC0.35 >40 at mAs max fT 4GHz
This figure shows the gummel plot of the device. From the slope 60mV/decade, we can tell it is similar to bipolar device. The current gain beta is more than 40 within mA range.

19. LBJT Harmonic Mixer RL OUT- OUT+ VRF+ VRF- Ii VLO- VLO+ M1 M2 VDD Q1
This is lateral bipolar version of harmonic mixer. The RF stage is replaced by the new device.

20. Noise Performance Large LO improves noise.
This is the noise performance. Still at 10kHz, the noise figure improves a lot compared to previous one.
Large LO improves noise.

21. Even Order Distortion frf
RF Signal
frf
BB Signal
Interference
IM2 (f2-f1)
a1x+a2x2+a3x3+… f1 f2
It is mainly introduced by layout asymmetry and device mismatch.
Since direct-conversion, the intermodulation components IM2 will fall into the demodulated signal spectrum.
Therefore, good IIP2 is required for homodyne receivers.
It is found that varying the loading resister or voltage bias can compensate the device mismatch and improve IIP2 significantly.

22. IIP2 Improvement IIP2=18dBm IIP2>40dBm Same DC bias Compensation
This is two tone testing. Due to device mismatch, IP2 is not so good. With additional offset voltage biasing at the RF input, the performance improves a lot.

23. LBJT Mixer Performance
Technology
TSMC 3M2P 0.35m
VDD 3V
Signal Gain
+15dB
DC offset suppression
>30dB
Noise 10kHz
<18dB
1dB compression point
>-20dBm
Input-referred IP3
>-9dBm
Input-referred IP2
>+40dBm
Power consumption
<2.2mW

24. Summary on Mixer Flicker noise free, corner frequency is below 10kHz.
DC offset free, more than 30dB DC offset suppression is achieved.
No LO leakage problem.
Sufficient IIP2 after bias compensation.
High gain and low power consumption.
Complete CMOS process.
Suitable for CMOS direct conversion applications.

25. Difficulties in FLEX Pager
FLEX 6400, 4FSK
-20
-40
-60 dB 10 5 -5
-10
kHz -1
12dB Eb/N0
High pass effect 10 -2
High pass corner (Hz) 10
Big Challenges
Narrow band modulation
Significant energy near DC
High pass filtering is not viable
DC offset problem
Flicker noise is significant
After solving the dc offset problem, let me move to the pager receiver. It can be seen from the figure that it is a kind of narrow band modulation. And it has significant energy near DC. High pass filtering is not viable. The right top figure shows that higher corner, the worse BER performance. DC offset is also the big problem. With larger DC offset, the BER performance degraded significantly. In addition, flicker noise is severe for this narrow band modulation. 10 -1
DC Offset Effect
BER 10 -2 4 8 12 16
Eb/N0 (dB)

26. 4-FSK Pager Receiver
45
AGC
LNA
DEMOD
VCO
RF: Zhaofeng
BB: Zhiheng
This is the block diagram of the pager receiver. The signal is amplified by LNA and mixed down directly by harmonic mixers. Because of the harmonic mixer, we need a 45 degree phase shift. The demodulated signal goes through AGC, LPF and is sent to the 4-FSK demodulator. Harmonic mixer is for time-varying dc offset. Peak detectors are used to cancel static DC offset. We used high front-end gain and current injection method to reduce the flicker noise with a compromise on linearity performance.
Fully differential architecture to reject substrate noise.
Harmonic mixers are used to solve time-varying DC offset.
Peak detectors are used to cancel static DC offset.
High front-end gain and current injection to reduce flicker noise.

27. LNA
Non-quasi-static phenomenon makes it unnecessary to do on-chip matching.
Off-chip matching by a single inductor and a balun.
930MHz
Both on-chip and off-chip inductive loads were tried.
Let me go to the individual blocks. LNA is constructed with differential cascoded transistors. The matching was done off-chip due to unpredictable non-quasi-static effect. Also off-chip matching provides better noise performance due to higher Q. Only one inductor and a balun is used. The matching achieves -20dB at the center frequency. For the LNA load, both on-chip and off-chip inductors were tried. On-chip for higher integration and off-chip for large gain and good noise figure.

28. Double Balanced Mixer
Double balanced harmonic mixers were used to improve the linearity and provide constant impedance to LNA. Current injection provides more than 20dB flicker noise reduction.
Improve the linearity; Provide constant impedance to LNA;
Current injection provides more than 20dB flicker noise reduction.

29. Ring Oscillator Half RF frequency, Provide 45 phase.
The differential 4-stage ring oscillator was designed to provide 45 degree phase shift. Notice that the oscillating frequency is the half of the RF signal. Source coupled logic was used for smaller swing and smaller coupling.
Half RF frequency,
Provide 45 phase.

30. Static DC Offset Cancellation
Zero-IF
4-FSK
Signal
Peak
Detector
Fmin200Hz
For static DC offset cancellation, the peak detector was used as the offset indicator. The peak difference of the differential signals equals to the DC offset. It was subtracted out at the output. The half of the peak detector was used for the peak detection. The minimum operating frequency is larger than 200Hz.

31. Performance Summary Pager receiver with off-chip ind
Maximum Gain: 62dB
Noise 14.5dB
Overall DC offset at LPF output: <1mV
(Signal: 400mV)
Power dissipation: 58mW
Technology: TSMC0.35mm 4M2P
Die area: mm2
Front-End Off-chip ind On-chip ind
RF/BB gain: dB dB
dB dB
dB dB
IIP3: dBm dBm
IIP2: dBm dBm
Operating frequency: MHz
LO frequency: 465MHz
IQ gain mismatch: < 0.3dB
IQ phase mismatch: < 5
RF/BB over LO/BB: > 54dB
Self-mixing free
Input matching: < -20dB
Power dissipation: mW
Baseband (Zhiheng)
AGC gain: dB~18.6dB
LPF: Pass-band gain-6.2dB, ripple 0.5dB (9kHz)
Stop-band attenuation  63dB ( 17.8kHz)
Offset cancellation: <2mV (under ±100mV input offset)
Input Referred Noise: 600nV/ @ 10kHz
Clock Recovery: Capture range > 550Hz
Power dissipation: 5.4mW (including all testing buffers)

32. Die Photo RF Front-End Base Band Circuitry[Zhiheng] DEMOD LPF AGC
45
AGC
LNA
DEMOD
VCO
DEMOD
LPF
AGC
Mixer
OSC
LNA
Base Band Circuitry[Zhiheng]
RF Front-End
Here is the die photo. RF front-end with off-chip inductor. RF front-end with on-chip inductor, and the base band circuitry. The chip was fabricated in a TSMC0.35 process.

33. Summary on Pager Receiver
Feasibility of direct conversion has been demonstrated.
Proposed harmonic mixing technique solves self-mixing induced DC offset problem successfully.
With the help of static DC offset cancellation, the total DC offset is less than 1mV at the receiver output.
The modified ZIFZCD 4-FSK demodulator functions correctly.
A 4-FSK FLEX pager receiver in a single chip has been implemented successfully.

34. Conclusion Circuit design for direct-conversion has been discussed.
DC offset: more than 30dB improvement
LO leakage: no longer a problem
Flicker noise: corner frequency is less than kHz due to lateral bipolar device.
IIP2: larger than +40dBm after bias compensation.
System on chip has been successfully demonstrated using CMOS direct conversion architecture.