1. EC board for JEM-EUSO Design investigations
S. Ahmad, P. Barrillon, S. Blin,
D. Cuisy, S. Dagoret, C. De la Taille,
F. Dulucq, R. Sliwa, J-L. Socha
Journées VLSI/PCB/FPGA/Outils - Session PCB – mercredi 25 juin 2010

2. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
JEM – EUSO
Satellite project (not yet approved) that should be installed on International Spatial Station (~ 2015)
International collaboration (East Asia, EU, US) supported by 3 spatial agencies (JAXA, NASA, ESA)
Multi-purpose experiment
Study of cosmic rays and their sources
Study of atmospheric physic
Study of meteors
Lightning study…
EECRｓ
X, γ,ν,p, e
UV, X, γ,ν
p, n, e
Charged
Particles
Ultraviolet photons
Plasma Discharge
Dust and Meteors
Night glow
Solar wind
The Earth
Atmosphere
Air shower
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

3. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
JEM – EUSO detector
Focal Surface
SPACIROC
(See S. Amhad talk)
Readout chip
PDM
5000 MAPMTs (8x8 pixels)
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

4. EC board – next generation PMF
Study of EC board has been asked to LAL
Power MAPMTs
SPACIROC location
Data transfer to the rest of electronic line
Starting point: PMF (PhotoMultiplier Front end) - Front end electronic for ATLAS luminometer (ALFA) used to readout 64 channels MAPMTs from Hamamatsu
3 PCB boards (3 x 3 cm) are used:
HV board: allows bringing high voltage to the MAPMT (64ch)
Passive board: roots signals to connectors on the edges of the board
Active board: readout and treatment of the PM output signals successively by the MAROC2 ASIC on one side and a Lattice FPGA on the other side.
See talk given 2 years ago
active board
passive board
Big insulating
Small insulating
lumi pmf HV 0715
lumi pmf passive
lumi pmf2 alpha
PMT
PMF exploded view
hv board
MAPMT H7546
from Hamamatsu
FPGA side
kapton cable
ASIC side
3.5 cm
PMT
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

5. Mechanical constraints (1)
Electronics + Supports +
Volume for Electronics (167 x 128 x 130)
Frame + MAPMT+ Electronics
PDM Frame
MAPMT
EC Base
PDM frame: 167mm x 167mm x 28.7mm
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

6. Mechanical constraints (2)
Considering all dimensions we have a really limited space available (in thickness) for the EC board (4-5 mm) + frame: ~ 12 mm
 Can not have 3 PCBs (like PMF)
130
167
128
192.4
28.7
MAPMT
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

7. Starting point: EC board dimensions
52.5 mm x 52.5 mm (frame: 55 x 55)
Hole dedicated to the rod used for fixing
Frame (drawings from
INFN Frascati)
LAL drawing for EC board
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

8. 64 channels MAPMT dimensions
Vacuum pipe present
for the prototype
removed for production
14 pins needed: dynodes 1 to 12 + GR + K
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

9. EC board design considered
Single thick PCB since 3 PCB-like is not possible because of space constraint
Readout ASIC in a BGA package mounted on the other side of the PCB
BGA looks like a good solution considering the tight space constraints
BGA should be chosen considering the foreseen (higher estimation) number of I/O and the space available
MAPMT pins inserted in the PCB into non-crossing holtites
1 connector would bring all signals (14) needed by the MAPMT
2 connectors (60 pins foreseen) would bring power to the ASIC and collect output signals
Easier to drive the signals to/from the 4 ASICs
Good connection reliability
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

10. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
BGA
144 pins BGA
(13 x 13 mm)
1 mm step
2 ways to connect
the chip inside BGA
Number of pins should be enough considering similar ASICs
Dimensions are reasonable and give more space to locate the connectors
R. Sliwa
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

11. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
Overall view
J-L Socha
CMS connector
22 signals + power
CMS connector
22 signals + power
Estimated from
frame drawing
HV connector
(14 lines)
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

12. PCB structure Length needed for MAPMT pins: 7 mm (5.6 mm on proto)
Example of PCB structure (mm)
Type of vias considered
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

13. MAPMT print + bottom view
Some of the pins (HV) are really close to the edges, we would need more space
rotated
x 4 and located in the considered design of the EC board
0.5 mm is the minimum distance between hole and edge of PCB
HV instability with PDM frame ?
8 pins would be on the edges… but only
2 could be used
 little modification of the frame design
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

14. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
Top view
Connector print
BGA print
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

15. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
Conclusion
First steps of EC board design:
Feasibility
non crossing holtites  only one company (pretend to) do it in France
chip in BGA
Dimensions taking into account:
MAPMT dimensions
BGA size
location for connectors
Some needs (length of PMT pins and size of the PCB)
Many other steps to come
single thick PCB (can mean large vias), ok for space ? …
This is a very innovative concept and challenging project. We don't have the experience return with this technology (thick PCB and non-crossing holtites)
We will need to try several options starting with a mockup version that would be useful to check feasibility mechanically and electronically (money expected to develop these various prototypes)
It looks like the only option that fits the JEM-EUSO space and spatial constraints and probably reliability
First adaptations of the EC frame have been applied following our comments
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

16. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
Changes on the frame
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

17. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
BACK-UP SLIDES
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

18. From where the 4mm come 6.5 – 2 – 0.5 = 4 mm MAPMT location
EC board location
Total thickness of the frame
6.5 – 2 – 0.5 = 4 mm
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

19. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
HOLTITE
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

20. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
PMF structure
The PCB part of the PMF is made of 3 boards (3 × 3 cm2) :
HV board: allows bringing high voltage to the MAPMT (64ch)
Passive board: roots signals to connectors on the edges of the board
Active board: readout and treatment of the PM output signals successively by the MAROC2 ASIC on one side and a Lattice FPGA on the other side.
A 60 points connector allows connection of the PMF with the mother board or the test board thanks to a kapton cable.
The 3 PCBs, the cable and the test board were developed at LAL, the mother board and the Lattice firmware at CERN.
MAROC side
Lattice side
Active board
HV board
Passive board
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

21. The HV board 2 layers (c1 and c2) PCB Brings high voltage to the PMT
Vacuum
Large insulating element C1 C2
HV cable
64 channels
MAPMT H7546
from Hamamatsu
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

22. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
The passive board
4 layers (c1, c2, c3 and c4) PCB
Routes signals from PMT to the connectors on the edge
Routing optimized to reduce cross-talk C1 C2 C3 C4
Holetites inserted and bonded on C1 side
Black connectors bonded on C4 side
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL

23. Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL
The active board
Challenging part of the project !
Design of a 10 layers printed circuit board with MAROC chip bonded (at CERN) directly on the PCB on one side and a FPGA/BGA on the other side.
Different types of crossing, blind and laser vias
Limited space available for the other components (connectors, capacitors, resistors) and the test points
MAROC located on 6th layer
Bonding wires connected to pads located on c1 (top) and c2 layers.
Top C2
25 juin 2010
Journees VLSI/PCB/FPGA/Outils - Session PCB - Pierre Barrillon - LAL