1. DHCAL PCB STUDY For RPC 1 m2 PCB SOLUTION
William TROMEUR, Hervé MATHEZ, Renaud GAGLIONE,
Imad LAKTINEH, Rodolphe DELLA-NEGRA
(CNRS IN2P3 IPNL)
Collaboration with LAPP and LAL

2. 1 m2 PCB MAIN SPECIFICATIONS
ASU PCB Design
24 x 64 1 sq cm pads
24 Hardrocs Asics chained
1 m2 PCB board :
6 ASUs
144 Hardroc Asics
DIF boards :
1 DIF for 1 ASU : 6 DIFs
1 DIF for 2 ASU : 3 DIFs
Buffered Signals
(Long Lines 1 m for Clock on 1 ASU):
Slow Control
Power_on
Control for Analog Readout
Digital Readout
Analog Readout :
All OUT_Q are connected together
EN_OTAQ switch on or off using DIF board and decoder

3. ASU PCB DESIGN 50 cm 36 cm Y X ASU to ASU ASU to ASU connector
GND Connector ASU to ASU on Y axis
HR1
HR24
ASU to ASU
connector
ASU to ASU
connector
36 cm
Buffers
(Other signals)
Buffers
(Clocks)
Power and Gnd
Connector
ASU to ASU
on X axis
DIF
connector
GND Connector ASU to ASU on Y axis
1536 pads on Bottom Layer
Buried and Blind Vias (Same as the last PCB with 4 HR)

4. 1 m2 PCB DESIGN 1 DIF for 2 ASUs DIF Board ASU to ASU Connection
Pad
Solder
9216 pads on Bottom Layer

5. 1 m2 PCB DESIGN
1 DIF for 1 ASUs

6. Pads to Hardroc interconnects are the same for the entire PCB
1 m2 PCB DESIGN
(Layers)
Layer 1 (TOP) : interconnect
Layer 2 : interconnect
Layer 3 : 3.3V Digital
Layer 4 : GND
Layer 5 : 3.5V Analog
Layer 6 : PADs to Hardroc
Layer 7 : GND
Layer 8 (BOTTOM) : PADs
Pads to Hardroc interconnects are
the same for the entire PCB
(hierarchical design)
Send the Layout to Fab next week

7. 1 m2 PCB SCHEMATIC

8. 1 m2 PCB SCHEMATIC
Change 3.3V dig
and 3.3V Ana
Add Pull-Up resistor

9. 1 m2 PCB SCHEMATIC

10. 1 m2 PCB SCHEMATIC

11. 1 m2 PCB SCHEMATIC

12. 1 m2 PCB SCHEMATIC

13. 1 m2 PCB SCHEMATIC

14. 1 m2 PCB SCHEMATIC