1. Implementing Instructions

2. Machine Cycle
Fetch Decode Execute

3. Architeture
High level architecture

4. Detailed View
Data/Address Paths
Not shown: Control signals

5. Special Purpose Registers
PC : Current Instruction Address
IR : Current Instruction
MAR : Address to get/store
MBR : Data to get/store

6. RTN RTN : Register Transfer Notation [r1]  [r3] + [r2]
r1 gets set to sum of values in r2 and r3
[PC]  [PC] + 4 PC gets set to sum of PC and 4
[r1]  [[MAR]] r1 gets set to the value in the memory location stored in MAR
[ALU:P]  [r1] The P input of ALU gets the value stored in r1

7. Fetch Step 1 Copy PC to MAR [MAR]  [PC] Step to next instruction
[PC]  [PC] + 4

8. Fetch Step 1 Copy PC to MAR [MAR]  [PC] Step to next instruction
[PC]  [PC] + 4

9. Fetch Step 2 Retrieve Intruction from memory [MBR]  [[MAR]]0x
Retrieve Intruction from memory
[MBR]  [[MAR]]

10. Fetch Step 2 Retrieve Intruction from memory [MBR]  [[MAR]]0x
Retrieve Intruction from memory
[MBR]  [[MAR]]
0xE59F100C

11. Fetch Step 3
Put instruction in IR
[IR]  [MBR]
0xE59F100C

12. Fetch Step 3
Put instruction in IR
[IR]  [MBR]
0xE59F100C
0xE59F100C

13. Fetch Summary
[MAR]  [PC] [PC]  [PC] + 4 [MBR]  [[MAR]] [IR]  [MBR]

14. Decode
Control unit reads opcode, sets control lines
0xE59F100C

15. LDR
Instruction represents:
LDR r1, x
0xE59F100C

16. Execute LDR Step 1 Copy Operand part of IR to MAR
[MAR]  [IR(Operands)] OR
[MAR]  [IR(Address)]
0xE59F100C

17. Selecting MBR Source
Any time two lines join, need a multiplexer:

18. Execute LDR Step 1 Copy Operand part of IR to MAR
0x100C
Copy Operand part of IR to MAR
[MAR]  [IR(Operands)] OR
[MAR]  [IR(Address)]
0xE59F100C

19. Execute LDR Step 2
0x100C
Get date from memory
[MBR]  [[MAR]]

20. Execute LDR Step 2
0x100C
Get date from memory
[MBR]  [[MAR]] 5

21. Execute LDR Step 3
Store to register
[r1]  [MBR] 5

22. Execute LDR Step 3
Store to register
[r1]  [MBR] 5 5

23. LDR Summary
[MAR]  [IR(Operands)] [MBR]  [[MAR]] [r1]  [MBR]

24. ADD
Instruction represents:
ADD r3, r1, r2
0xE

25. ADD Step 1
Store to register
[ALU:P]  [r1]
[ALU:Q]  [r2] 4 3

26. ADD Step 1
Store to register
[ALU:P]  [r1]
[ALU:Q]  [r2] 4 3 4 3

27. ADD Step 2 Write result to register [r3]  [ALU:P] + [ALU:Q] OR
[r3]  [r1] + [r2] 4 3

28. ADD Step 2 Write result to register [r3]  [ALU:P] + [ALU:Q] OR
[r3]  [r1] + [r2] 7 4 3

29. ADD Summary
[ALU:P]  [r1] [ALU:Q]  [r2] [r3]  [ALU:P] + [ALU:Q] OR [r3]  [r1] + [r2]

30. Immediates
Instruction represents:
MOV r2, #4
0xE

31. Move Immediate Step 1 Move operand bits to r2 [r2]  [IR(Operands)]
0xE

32. Move Immediate Step 1 Move operand bits to r2 [r2]  [IR(Operands)]
0xE
0x0004

33. Add Immediate
Instruction represents:
ADD r2, r1, #4
0xE 3

34. Add Immediate Step 1 Move immediate to Q Move r1 to P
[ALU:Q]  [IR(Operands)]
[ALU:P]  [r1]
0xE 3

35. Add Immediate Step 1 Move immediate to Q Move r1 to P
[ALU:Q]  [IR(Operands)]
[ALU:P]  [r1]
0xE 3 3
0x0004

36. Add Immediate Step 2 Store result to r3 [r2]  [ALU:P] + [ALU:Q] 3
0x0004

37. Add Immediate Step 2 Store result to r3 [r2]  [ALU:P] + [ALU:Q] 7 3
0x0004

38. Add Immediate Summary [ALU:Q]  [IR(Operands)] [ALU:P]  [r1]
[r2]  [ALU:P] + [ALU:Q]

39. Branches Instruction represents BEQ foo Where foo is at 2024
0xEA612024

40. Branches
EQ means Z(ero) flag is set
If Z, set PC to 2024
0xEA612024

41. Branches Possibility 1 If Z, set PC to 2024
RTN: If [Z] = 1 THEN [PC]  [IR(Operands)]
0xEA612024
1010

42. Branches Possibility 1 If Z, set PC to 2024
RTN: If [Z] = 1 THEN [PC]  [IR(Operands)]
0x2024
0xEA612024
1010

43. Branches Possibility 2 If Z, set PC to 2024
RTN: If [Z] = 1 THEN [PC]  [IR(Operands)]
0xEA612024
0010