1. CSE 575 Computer Arithmetic Spring 2003 Mary Jane Irwin (www. cse. psu
CSE 575 Computer Arithmetic Spring Mary Jane Irwin (
This set of slides needs more work as well.

2. A Binary Square Root Algorithm
Q square root
Q0 = 0
Z radicand = 11810
0 1
q3 = 1
Q1 = 01
 101 ? No so choose 0
q2 = 0
0 0 0
Q2 = 010
 1001 ? Yes so choose 1
choose radicand digit so that (4Qi + new radicand digit) does not exceed the partial remainder
10^ = 118 (base 10)
q1 = 1
Q3 = 0101
 ? No so choose 0
q0 = 0
Q4 = 01010
= 1010
S remainder = 1810

3. Shift/Subtract Square Root
Square root as repeated shifts & subtracts .
Q square root .
Z fixed point radicand
1  Z < 4
partial
remainder
array
S scaled remainder
(Z - Q2)

4. Restoring Square Root Recursion
Notation
Z radicand z1z0 . z-1z-2 … z-l (1  Z < 4)
Q square root q-1q-2 … q-l (1  Q < 2)
S scaled rem s1s0 . s-1s-2 … s-l (0  S < 4)
Basic recurrence
S0 = Z – 1, Q0 = 1, Sl = S and Ql = Q
Sj = 2Sj-1 – q-j(2Qj jq-j) where q-j  (0,1)
(Qj-1 =  2-kq-k for k=0 to j-1)
Qj-1 is the partially developed root up to its –j-1th digit
S1 = 2S0 – q-1(2Q q-1) = 2(Z-1) – q-1 (2* q-1)
The amount subtracted from 2Si-1 is either 2Qj j if q-j is 1 or 0 if q-j is 0
Write highlighted iteration on the board for reference in later slides

5. Square Root Digit Selection
First perform the trial subtraction
STj = 2Sj-1 – (2Qj j)
0 if STj < 0  Sj = 2Sj-1
q-j =
1 if STj  0  Sj = STj
stop when Sj = 0 or after l iterations
Really doing
if STj < 0 then q-j= 0 & Sj = STj + (2Qj j)
if STj  0 then q-j= 1 & Sj = STj
restore op
average number of operations in binary
n subtracts (one per digit)
n/2 add (restores) on average
n one bit left shifts
3n/2 add/subtract cycles
NO WAY TO PARALLELIZE since quotient digits are formed serially

6. Binary Square Root Example
Z radicand
S0 = Z-1
q0 = 1
Q0 = 1.
1 0. 1
-(2*(1.)+2-1)
q-1 = 0
Q1 = 1.0
restore
S1 = S0
For lecture
-(2*(1.0)+2-2)
q-2 = 1
Q2 = 1.01 S2
-(2*(1.01)+2-3)
q-3 = 0
Q3 = 1.010
restore
S3 = S2
. . .

7. Left Shift Serial Square Root
Shift left
radicand
square root
Z or S
Z or Q
scaled remainder
q-j
2Qj-1
n bit
adder
n bits
Control
sequencer and root select logic 
2-jq-j
Add/subt
sign

8. Nonrestoring Square Root
Can develop in a similar way a nonrestoring square root algorithm where q-j  (-1,1) and the resulting root can be converted on-the-fly to a binary format
Expand this next time!

9. Higher Radix Square Root
To speed up square root can use a similar higher radix approach as used in (SRT) division
Sj = rSj-1 – q-j(2Qj-1 + r-jq-j)
The problem is, as expected, square root digit selection (a table lookup process). With proper care the same lookup table can be used for QDS and RDS (example for base 4)
Division: Sj = 4 Sj-1 – q-jD
SqRoot: Sj = 4 Sj-1 – q-j(2Qj jq-j) with q-j=[-2,2]
Expand this next time!

10. Square Root by Convergence
Newton-Raphson method
f(X) = X2 –Z that has a root at X = Z
Basic iteration of Xi+1 = 0.5(Xi + Z/Xi)
Requires a division, an addition, a bit right shift
Initial guess of X0 = 2
Xi will remain in range 1  Xi <2
Better initial guesses give faster convergence
Quadratic convergence from above
Many other schemes
Find reciprocal of Z and then multiply by Z to obtain Z using f(X) = 1/X2 – Z that has a root at X = 1/Z

11. Decimal Example Find Z where Z = 2.410 (Z = 1.549 193 . . .)
X0 = (read from table) = 0  10-1
X1 = 0.5(X /X0) = 1  10-2
X2 = 0.5(X /X1) = 2  10-4
For lecture
X3 = 0.5(X /X2) = 2  10-8

12. Nonrestoring Array Square-Rooter
z-1
z-2 1 1
xor
z-3
z-4
q-1 1 FA
z-5
z-6
q-2 1
derived directly from the dot notation for nonrestoring square root
the controlled add/subtract cell depend on the sign of the preceding partial remainder
z-7
z-8
q-3 1
q-4
s-1
s-2
s-3
s-4
s-5
s-6
s-7
s-8

13. Key References
Agrawal, High-speed arithmetic arrays, IEEE Trans. on Computers, 28(3): , 1979.
Ercegovac and Lang, Division and Square Root: Digit Recurrence Algorithms and Implementations, Kluwer, 1994.
Montuschi and Mezzalama, A survey of square rooting algorithms, Proc. IEEE, Vol 137, pp , 1990.
Parhami, Computer Arithmetic, Oxford Univ. Press, 1999.
Schwartz and Flynn, Hardware starting approximation methods and its application to the square root operation, IEEE Trans. on Computers, 45(12): , 1996.
Zurawski and Gosling, Design of a high-speed square root, multiply and divide unit, IEEE Trans. on Computers, 36(1):13-23, 1987.