1. Early Stage Researcher: Panos Neroutsos
November 2014
Project title: Advanced monitoring for the Serial Link Processor of the ATLAS Fast TracKer (FTK) system.
Project Type: MC-IAPP Industry Academia Partnerships and Pathways
Project Name: Fast Tracker for Hadron Collider Experiments (FTK)
Project Code:
1st EU Mid-Term Review Meeting
7th November 2014
Early Stage Researcher:
Panos Neroutsos

2. The monitoring module: Design specs
Work on WP 1: Prototype Construction & Production validation
The aim of this module is the detection of the synchronization losses (Lost Sync error) mostly at the Hit Chip in the AMBSLP.
The End event values contained in the End Event words identified on the 12 input links must be the same. We need to set a End Event Reference word to which all the others words are compared.
The current design is an evolution of Dimitris Dimas’ work. New features have been added to the algorithm:
The End Event Reference word was simply taken from Bus 0, now it is chosen by majority vote logic → most frequent value between the 12 input links.
One counter on each Hit Bus monitors how many losses of synchronization each bus had. Useful flags and signals indicate the status of the buses.
Design is generic and can be used in different boards in the FTK system.

3. The monitoring module: Majority vote and changes
Process of majority vote algorithm:
1. Set of comparisons for 12 bus input → Array
2. Increment counters if equal respectively on each bus for each pair combination.
3. Find max value and how many times is repeated → most common value
4. Find index(es) of the most common value
The module is designed to accept 12 or 8 input buses of generic bit length for future changes of the format of the words and the end event tag ID.

4. Spy Buffers Freeze logic: Current task
Our work is towards the implementation of a wrapper file to the freeze signal of the SpyBuffers.
The write operation is stopped to preserve the data inside the spy buffers when a freeze signal is asserted.
Checking the loss of synchronization errors from the other modules and the end event tag on each bus controlling the freeze signal.
A handshake is implemented between the Control Chip and the Hit Chip in order to notify each other when the freeze signal is active due to synchronization errors or the end event errors.
Two 2 extra bits are used to describe the error code to justify the reason of the freeze signal.

5. Current tasks and objectives
During my PRISMA:
Crate AUTH Thessaloniki and Prisma Electronics.
Testing and debugging current firmware for the AMBSLP. Verification of the current firmwares.
Initial setup with AMBSlim and AMBSLP with MiniLAMBs.
MS.c Thesis title: “Advanced monitoring for the Serial Link Processor of the ATLAS Fast TracKer (FTK) system.”
Publications:
A.Annovi, A.Andreani, R.Beccherle, M.Beretta, N.Biesuz, W.Billereau, J.M Combem, M.Citterio, S.Citraro, A.Colombo, F.Crescioli, D.Dimas, S.Donati, P.Giannetti, K.Kordas, A.Lanza, V.Liberali, P.Luciano, D.Magalotti, P.Neroutsos, S.Nikolaidis, M.Piendibene, E.Rossi, A.Sakellariou, J. Shojaii, C.L. Sotiropoulou, A. Stabile, P. Vulliez, “The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS”, Tipp 2014 Third International Conference on Technology and Instrumentation in Particle Physics.

6. Training & Experience
Further experience with Xilinx tools. Developed skills on VHDL coding and simulation.
Experience with hardware debugging.
Collaboration with highly skilled team members of the FTK team.
Participation in:
3rd Workshop on Modern Circuits and Systems Technologies (MOCAST) 14 March 2014.
HiPEAC High Performance and Embedded Architecture and Compilation, CSW Athens, October 2014.
Prisma Electronics: Training in Athens.
FTK collaboration gives me the motivation to expand my knowledge and skills on hardware design issues and high energy physics experiments.

7. Thank you for your attention!