1. By: Mohammadreza Meidnai Urmia university, Urmia, Iran Fall 2014
Pipelined FIR Filter
By: Mohammadreza Meidnai
Urmia university, Urmia, Iran
Fall 2014

2. Content:
Filter
Digital filtering
FIR filter
Pipelining
Pipelined FIR

3. Transfer functions of four standard ideal filters

4. Ideal low-pass filter approximation

5. The ideal filter frequency response can be computed via inverse Fourier transform. :The four standard ideal filters frequency responses are

6. Basic concepts of digital filtering
The analog input signal must satisfy certain requirements. Furthermore, on converting an output digital signal into analog form, it is necessary to perform additional signal processing in order to obtain the appropriate result.

7. Calculations in digital filtering typically involve multiplying the input values by constants and adding the products together.

8. Types of digital filters:
Filters can be classified in several different groups, depending on what criteria are used for classification.
The two major types of digital filters are finite impulse response digital filters (FIR filters) and infinite impulse response digital filters (IIR).

9. FIR digital filter:
In signal processing, a finite impulse response (FIR) filter is a filter whose impulse response (or response to any finite length input) is of finite duration, because it settles to zero in finite time.
The impulse response of an Nth-order discrete-time FIR filter lasts exactly N + 1 samples (from first nonzero element through last nonzero element) before it then settles to zero.

10. FIR filters are digital filters with finite impulse response
FIR filters are digital filters with finite impulse response. They are also known as non-recursive digital filters as they do not have the feedback.
FIR filter transfer function can be expressed as:

11. FIR filter output samples can be computed using the following expression:
h[k]: impulse response of system

12. FIR filter realization
Direct realization

13. FIR filter realization
Direct transpose realization
This structure is beneficial compared to the direct form as the delay elements (z−1) can be used as pipeline registers for the structural adders.

14. FIR filter realization
Optimized realization
The symmetry of the coefficients of FIR filter frequency response can be expressed by equation below:

15. Optimized realization for odd frequency response

16. Optimized realization for even frequency response

17. Pipelining
In computing, a pipeline is a set of data processing elements connected in series, where the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion; in that case, some amount of buffer storage is often inserted between elements
Pipelining is a natural concept in everyday life, e.g. on an assembly line. Consider the assembly of a car: assume that certain steps in the assembly line are to install the engine, install the hood, and install the wheels (in that order, with arbitrary interstitial steps). A car on the assembly line can have only one of the three steps done at once. After the car has its engine installed, it moves on to having its hood installed, leaving the engine installation facilities available for the next car. The first car then moves on to wheel installation, the second car to hood installation, and a third car begins to have its engine installed. If engine installation takes 20 minutes, hood installation takes 5 minutes, and wheel installation takes 10 minutes, then finishing all three cars when only one car can be assembled at once would take 105 minutes. On the other hand, using the assembly line, the total time to complete all three is 75 minutes. At this point, additional cars will come off the assembly line at 20 minute increments.

18. Pipelining mean in filters field:
Pipelining transformation leads to a reduction in the critical path, which can be exploited to either increase the clock speed or sample speed or to reduce power consumption at same speed.
While pipelining reduces the critical path, it leads to a penalty in terms of an increase in latency. Latency essentially is the difference in the availability of the first output data in the pipelined system and the sequential system.
For example if latency is 1 clock cycle then the k-th output is available in (k + l)-th clock cycle in a 1-stage pipelined system.

19. PIPELINING OF ADDER GRAPHS
Adder graph for the coefficient set {480, 512, 846, 1020}
e.g : node 15 is realized by shifting the input x by 4 bit and subtracting the unshifted input: 15x = 24x − 20x

20. The pipelined adder graph after cut-set retiming:
the maximum clock frequency of the structure in this Fig can be approximately three times higher than for the original structure if inputs and outputs are registered

21. References
Martin Kumm and Peter Zipf, ‘High Speed Low Complexity FPGA-based FIR Filters Using Pipelined Adder Graphs’, /11/$26.00 c 2011 IEEE
Zoran Milivojevi.: 'Digital Filter Design', MikroElektronika 2009