1. Instruction Encoding Synthesis for Architecture Exploration using Hierarchical Processor Modes
Achim Nohl, Volker Greive, Rainer Leupers, Oliver Schliebusch, and Heinrich Meyr

2. Outline Abstract Introduction Variable Length Opcodes Opcode Synthesis
Hierarchical Processor Models
Local Operation Encoding
Global Optimization
Results
Conclusions

3. Abstract Instruction encoding generation technique
For ASIP’s architecture exploration
Tedious manual specification of opcode
這篇paper主要是針對ASIP的architecture提出一個對instruction opcode encoding的方法。
因為傳統要產生一個processor的simulator之前，都必須以人工先定義好opcode。所以作者提出一個自動assign的方法來改善這的問題。

4. Introduction ASIP Iterative architecture exploration
Stepwise refinement
Simulation/profiling
Various modeling abstraction levels
From untimed high-level language
To cycle-acurate RTL HDL synthesis models

5. Introduction (cont.) Need to provide some detailed information
Binary instruction encoding
For profiling
Assembler
ISA simulator
Irrelevant before the RTL modeling stage
Instruction encoding synthesis technique

6. Variable Length Opcodes
Instruction
opcode
Operands
NOP
0000
xxxxxxxxxxxx
xxxxxxxxxxxxx
ADD
0001
src1
src2
dest
001
SUB
0010
010
LOD
0011
address
011
STO
0100
100
MOV
0101
xxxx
src
xxx OR
0110
1100
AND
0111
1101
LSH
10XX xx
shift
1110 x
JMP
11XX
offset
1111
Simple way: fixed-length opcode
左圖有些沒用到，就用don’t care
右圖有些就用variable-length opcode

7. Variable Length Opcodes (cont.)
Instruction encoding synthesis problem
Input : instruction-set S={I1,…,In}
Result : maxj=1…n(|Oj| + |Fj|) is minimal
Oj : a unique opcode
Fj : total operand field length Fj
Not “flat” ISA model
Above problem is used as a subroutine

8. Opcode Synthesis … 1 n1 = 15 15 p1 = 1 16 1 n0 = 4 15 Package i N=4 32 1
Operand length w 13 12 11 7
# instructions n 4 6 15
# distinction Instr. p
Opcode #1”
Opcode #15”
Opcode #16”*
7 bit operand
Opcode 1’
don’t care
Opcode 4’ …
* distinction opcode
package 0, n=4, w=0
package 1, n=15, w=7 1
n1 = 15 15
p1 = 1 16 1
n0 = 4 15

9. Opcode Synthesis Algorithm comprise two passes First (right-to-left)
Second (left-to-right)

10. Hierarchical Processor Models

11. Hierarchical Processor Models (cont.)

12. Local Operation Encoding
A Group is considered as a micro-instruction-set and can be automatically encoded using the algorithm presented in section 4.

13. Local Operation Encoding (cont.)21

14. Local Operation Encoding (cont.)
Locally unused

15. Global Optimization

16. Global Optimization (cont.)

17. Global Optimization (cont.)

18. Results

19. Conclusions Automatic instruction encoding Three method
In hierarchical processor
Three method
Local
Global
hybrid
Integrated in a processor design environment