1. Space vs. Speed: Binary Adders

2. Binary Adders
VHDL Adder
Carry Lookahead Adder

3. 4-Bit Adder C A B S

4. Adder in VHDL entity adder is port (
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
sum: out STD_LOGIC_VECTOR (3 downto 0);
carry: out STD_LOGIC );
end adder;

5. std_logic_arith.vhd

7. Ci
AiBi 00 01 11 10 1 1 1 1 1
Ci+1
Ci+1 = Ai & Bi
# Ci & Bi
# Ci & Ai

8. std_logic_unsigned.vhd

10. adder.vhd

11. Binary Multiplier 2 bit by 2 bit Half Adders are Sufficient
Since there is no Carry-in
in addition to the two inputs
to sum

12. Binary Multiplier
4 bit by 3 bit
4 bit by 3 bit
yields
7 bit result

13. Binary Adders
VHLD Adder
Carry Lookahead Adder

14. Carry Lookahead Adder C2 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
C3 = G2 + P2(G1 + P1 (G0 + P0C0))
= G2 + P2(G1 + P1 G0 + P0C0)
= G2 + P2G1 + P2P1G0 + P2PlP0C0
G0-3 = G3 + P3G2 + P3P2G1 + P3P2PlG0
P0-3 = P3P2PlP0

15. Ripple Carry Adder (4-bit)

16. Typically, longest delay path through n-bit ripple carry adder is 2n + 2
Tends to be one of the largest delays in a typical computer design
Counts as 2 gate delays 2 2 4 1 3 4 1

17. 4 4 2 6 5 6 4

18. 6 4 6 4 2 8 7 8 6

19. 8 6 4 8 6 4 2 10 9 10 8

20. 8 10 6 4 10 8 6 4
10 Gate Delays
16-bit Adder Gate Delays
64-bit Adder Gate Delays

21. Carry Lookahead Adder
Uses Propogate and Generate signals to “lookahead” for incoming carry signals
More complicated hardware configuration
Substantial decrease in gate delays

22. Ripple Carry
PFA: Partial Full Adders
Carry
Lookahead

23. Propagate. P = A xor B. If P = ‘1’ then the carry is “propagated”
Propagate P = A xor B If P = ‘1’ then the carry is “propagated” through. If P = ‘0’ then the carry is not “propagated” through.
Generate G = A and B
If G = ‘1’ a carry is “generated” regardless
of the carry bit.

24. For final carry determination, the Propagate signal is ANDed with the Carry Out and the Generate signal is ORed to the resulting signal. G P
Cin
Cout
Cin A B
Cout S
0 0
0 1
1 0
1 1
P G

25. Cin A B
Cout S
0 0
0 1
1 0
1 1
P G
Always Generate a Carry for A = 1, B =1
Cin A B
Cout S
0 0
0 1
1 0
1 1
P G
Propagate the Carry in

26. Cout

27. 2 4 1 2 4 3
Cout

28. 2 4
PFA For Bit # 1 1 2 4 1 3 4 2 2 3 2 3 1 4 2 1 2
Cout 3 2 3 1 4 2

29. Bit #2
Bit #1 2 2 4 6 1 1 4
Bit #4
Bit #3 2 2 6 6 1 4 4

30. Significant Delay Reduction
4 - bit Ripple: 10 Delays CLA: 6 Delays CLA level: 1*4 + 2 = 6
16 - bit Ripple: 34 Delays CLA: Delays CLA levels: 2*4 + 2 = 10
64 - bit Ripple: 130 Delays CLA: 14 Delays CLA levels: 3*4 + 2 = 14
But at the expense of a significant increase in the number of gates used by the circuit