1. environment infrastructure
General verification
environment infrastructure
and the verification of
the Ethernet1G peripheral device

2. Verilog as an HDL design language
Hardware Description Languages, or HDLs, are languages used to design hardware with.
they contains the capability to describe the function of a piece of hardware independently of the implementation .
A special compiler compiles the high language into flops and gates for production.

3. Verification, why? 1 bug = = 0.5 million US$
Silicon chips are very difficult to debug
Concept checking

4. E language as a verification language
1. Strong generation capabilities
2. Easy to use coverage data base
3. Strong temporal capabilities
4. Dynamic inheritance
5. Integrated industrial standard HDL simulators API
6. Build in test reconstructing capabilities

5. Directed test methodology
Defining feature list (spec)
Writing test plan
Designing a test per feature
Implementing a test per feature
Debugging the tests
Debugging bugs in the DUT

6. Random input generation methodology
Covarage data base
Score
board
Generation
Engine
Verification environment
DUT

7. Random input generation benefits
Reaches most of the wanted inputs and scenarios very quickly
Coverage items are easier to implement than tests
Gives the verification engineer a hole image of the DUT bug status quickly
In the future:The generator will take the coverage status as an input (loop back) and the process will converge automatically

8. The similarities between verification environments
Configuration object: Registers mirror
Test modes: environment operation flags
Injectors and collectors(eVCs)
Test terminating mechanism
Scoreboards: checking objects
Basic flow: signals init , reset , configuration, test special scenario and termination

9. Network processor structure
Protocol
processor
FLASH
Processor bus
DMA
External
memory
Network
processor
Network
processor
Peripheral bus
Hdlc
serial
ATM
serial
Ethernet
serial
TDM
serial
POS
serial

10. Ethernet1G verification environment structureRX
scoreboard RX NP RX
DMA
Ethernet
injector RX
device PP
Ethernet
collector TX
device TX NP TX
DMA TX
scoreboard

11. Results
Coverage:100%
coverage items where defined by HDL engineers on implementation and verification engineers on environment inputs
Bugs: 8 bugs found