1. Readout Electronics and Data Acquisition System of the MicroBooNE Experiment
Bo Yu, substituting for Hucheng Chen
On behalf of the MicroBooNE Collaboration
May 12th, 2009

2. 2009 IEEE Real Time Conference
Outline
MicroBooNE Experiment
Liquid Argon Time Projection Chamber (LArTPC)
Readout Electronics & DAQ System
Readout Architecture
Front-end Cryogenic Electronics
Online Data Reduction in FPGA
DAQ System
Outlook & Summary
DUSEL LArTPC
2009 IEEE Real Time Conference

3. MicroBooNE (Booster Neutron Experiment)
A 70 ton fiducial volume LAr TPC on the Booster Neutrino Beamline (BNB) at FNAL
Collaboration formed in 2007
10 univ+labs/50 phys+eng.
Under design phase and DOE CD-1 later this year
Low energy phenomena and excess observed by miniBooNE
Precision measurements of “golden” nm CCQE channel:
Possibility of CCQE measurements from intrinsic ne
Background for oscillation searches: NCpo, photonuclear events
2.5m 500V/cm
3 Readout wire planes
2 induction planes (U,V at ±60°from vertical)
1 collection plane (vertical wires, 2.5m long)
30 PMTs for T0 determination
Evacuable single vessel containment
3.8m ID, 12m long
Readout based on “cold” preamplifiers
JFET based discrete
~10,000 channels
Warm feedthroughs
Bi-phase purification system
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4. 2009 IEEE Real Time Conference
MicroBooNE
On-axis BNB
8 GeV protons on Be target
Focusing horn: p+, K+
Decay channel 50m
450m dirt
2-3x1020 POT/year
3-2 years running (6x1020 POT)
Proposed MicroBooNE site
Off-axis NUMI
110 mrad off NUMI target
4x1020 POT/year
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5. What is Liquid Argon Time Projection Chamber?
Unique detectors, true “electronic” bubble-chambers
High precision measurements combined in one technology
Tracking and Imaging (voxel size limited by diffusion)
Precision Calorimetry
Particle Identification (dE/dx meas. on the collection wire plane)
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6. Why LAr TPC detectors for neutrino and nucleon decay physics?
Neutrino Oscillation Physics
Significantly more sensitive (~x6) than Water Cherenkov detectors (i.e. smaller volumes for same physics reach)
More powerful background reduction ne
Proton Decay Search
Sensitive to other decay channels (e.g. p nK)
Extend sensitivity beyond Super-K limits with >5kton detectors
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7. MicroBooNE Readout Electronics
Cold Preamp. Motherboard
JFET discrete quad preamplifier
Intermediate Amplifier Board
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TPC Readout Board

8. Cryogenic Front-End based on JFET
Technology mature and available as of today
Reliability issues requires a careful choice of component and high-reliability design and assembly
Ceramic hybrid with co-fired traces and surface mount components properly tested
Several years of experience
Helios-NA34:
576 preamplifiers
Operations: 4 years, multiple cool-downs
Failure: 1
NA48:
Preamplifiers in LAr: 13,000
Operated at very high electric field
Failures: ~50 because of a HV accident in Negligible failures after that
Always kept at cryogenic temperature
Late 80’s
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9. Cryogenic Electronics Setup
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10. JFET Preamplifier Noise
In JFETs majority carriers
in the channel are electrons
CARRIER FREEZOUT:
Donor levels are ~40-50mV below band conduction, so a further reduction of temperature causes more and more electrons to fall in their donor energy levels.
In CMOS the conducting channel in
Enhancement mode is formed by
inversion (energy band
bending at the Si/SiO2 interfaces)
At high doping concentrations mobility increases and reaches a max., then decreases due to impurity scattering as the temperature of the lattice is reduced compared to the electron temperature
Bulk mobility increases as
temperature is reduced.
Transconductance also.
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11. 2009 IEEE Real Time Conference
Online Data Reduction
Dual Running Modes
Beam trigger mode
A total of 4.8ms (1 full drift time before and 2 after the trigger) of data are recorded without data loss
Supernova mode
All data undergo lossy data reduction and are buffered for one hour awaiting a potential supernova alert from other sources
Large Volume of Data
~10,000 readout channels
Utilize high density multiple channel ADC (AD Octal, 12-bit)
Each channel is digitized individually at 16MHz
~240GBytes/s instantaneous data throughput
Data Reduction
Online down-sampling
Shaper – 1µs peaking time
16MHz ADC data down-sampled to 2MHz
Lossless data reduction – Huffman coding
Lossy data reduction – Dynamic decimation
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12. A Case Study – BO TPC Detector
Slow variation of 5MHz raw data
Difference between two consecutive samples calculated
More than 99% differences are within -+3.
Shorter codes (1-7 bits) are assigned to differences with higher probability (in this case -3 to +3)
Any differences outside +-3 use 16 bits
In typical events, coding rate is ~1.5 bits/sample
U(n+1)-U(n)
Count
Probability (P)
Code
No. of bits (N)
P*N
-4 and others 11
Full 16 bits word 16 -3 45
111110 6 -2
358
1110 4 -1
9681 10 2
40867 1 +1
10145
110 3 +2
298
11110 5 +3
8.142E-05 7
total
1.00
1.53
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13. Huffman Coding (Lossless Compression)
U(n+1)-U(n)
Code
-4 and others
Full 16 bits word -3
000001 -2
0001 -1 01 1 +1
001 +2
00001 +3
Huffman codes are self-punctuated, i.e., an 1 is always the code end.
We pack the Huffman codes into 16-bit data words for additional fault recovery ability at the cost of reduced compression efficiency.
DD=0: 5M samples/s
DD=1: (5/16) M samples/s
Regular ADC data when
U(n+1)-U(n) is outside +-3 DD
ADC value (13-bit)
Reserved 1 X
Huffman Coded 1 1 1 1 1 1 1 -1 +1 +2
Padding or
Continue to
Next Word
In this example, 6 differences of the data samples are packed in the 16-bit data word.
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14. Dynamic Decimation (Lossy Compression)
5MHz raw data
(5/16)MHz dyn. dec.
Only small time intervals must be sampled at 5MHz
Most time intervals can be sampled with lower frequency, e.g., (5/16)MHz without losing useful information. (These wire*time areas are marked with lighter color in the lower left picture)
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15. Dynamic Decimation & Huffman Coding
Dynamic Decimation reduces number of samples by factor of 10.
Huffman Coding reduces number of bits from raw data by factor of 10.
When cascaded, the combination reduces number of bits by factor of 60.
Dynamic
Decimation
Huffman
Coding N
N/10.6
N/60
N/10.7
The blocks for dynamic decimation and Huffman coding have been test designed, compiled and simulated at 250 MHz in an Altera Cyclone III FPGA device
The logic element usage of these two blocks is very small compared to available resources in FPGA ( out of 39600)
Device: EP3C40F484C6, $129, Logic Elements Available
Logic Element Usage
Dynamic Decimation
217
Huffman Coding
245
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16. MicroBooNE DAQ System Architecture
Inside Crate
16 Front End Modules (FEM)
1 or 2 Transmit Module (XMIT)
Dataway on custom backplane
Dataway
The XMIT module initiates the token passing
FEM receives token, passes data to the dataway
FEM sends token to next one when it has no more data to transmit
Dataway could run at 640MBytes/sec for deadtimeless readout
SEB (sub event buffer)
Off the shelf PC
Data buffer, data checking, error handling etc.
Optical receiver module
Two 3.125Gbps optical links, can service two crates
PCI Express 4 lanes plug in card, 10Gbps throughput
DMA operation to send data to memory
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17. Dead Time Less Front End Module
FEM
Designed to take both beam trigger event and supernova data
Organize ADC data as frames
Data is written in time order, read in channel order to improve data reduction efficiency
Grouping/processing of the frame depend on whether it is beam trigger event or not
Data Flow
Processed events flow to the PC in separate paths
Two separate token passing dataways to separate the traffic flow
Keep neutrino and supernova events flow as independent as possible
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18. Beyond MicroBooNE: DUSEL
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19. Beyond MicroBooNE: CMOS Cold Electronics R&D
Operating at LAr temperatures (~90K)
Multiplexed architecture
Multiplexing may be performed in two steps, analog and digital, at appropriate locations within the cryostat
MUX>100
With highly multiplexed readout, cost vs. channel count curve flattens
Low noise, low power
Performance characterization as function of T of existing processes
Develop models for cryogenic operation to be used for subsequent design optimization
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20. 2009 IEEE Real Time Conference
Summary
LArTPC is a promising detector technology for neutrino long baseline experiments and nucleon decay searches
Cryogenic electronics, closed to the detector elements is critical to ease scaling issues
MicroBooNE will be the first running neutrino experiment to use a specific implementation of cryogenic front-end
JFET preamplifiers have been characterized in temperature and perform as expected
A strong R&D program to develop a low noise, low power ASIC with high multiplexing factor is required and has just started
MicroBooNE readout electronics and DAQ system
Readout architecture and data flow are well defined to accommodate the different running modes
Many electronics parts have been prototyped
Data reduction techniques in FPGA are actively studied
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21. MicroBooNE JFET Preamplifier
2009 IEEE Real Time Conference