1. ENGR 212 / CSCI February, 2003
Unless otherwise indicated these slides are taken from John Wakely’s
Stanford EE 121, Digital Design Laboratory

2. CMOS NAND Gates
Use 2n transistors for n-input gate

3. CMOS NAND -- switch model

4. CMOS NAND -- more inputs (3)

5. Inherent inversion.
Non-inverting buffer:

6. 2-input AND gate:

7. CMOS NOR Gates
Like NAND -- 2n transistors for n-input gate

8. NAND vs. NOR
For a given silicon area, PMOS transistors are “weaker” than NMOS transistors.
NAND
NOR
Result: NAND gates are preferred in CMOS.

9. Limited # of inputs in one gate
8-input CMOS NAND

10. Fancy stuff
CMOS AND-OR-INVERT gate