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積體電路元件與製程 半導體物理 半導體元件 PN junction CMOS 製程 MOS 元件.

Published byMaximilian Lloyd Modified over 6 years ago

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Presentation on theme: "積體電路元件與製程 半導體物理 半導體元件 PN junction CMOS 製程 MOS 元件."— Presentation transcript:

1 積體電路元件與製程 半導體物理 半導體元件 PN junction CMOS 製程 MOS 元件

2 ELECTRICAL CONDUCTION IN SOLIDS PROPERTIES OF THE MATERIALS
MOS Device ELECTRICAL CONDUCTION IN SOLIDS PROPERTIES OF THE MATERIALS MOS Device Behavior Sub-Micron MOS Transistor

3 ■ ELECTRICAL CONDUCTION IN SOLIDS

4 Energy Gap in solids

5 Fermi-Dirac distribution function for three different values of temperature

6 Carrier Density

7 Intrinsic and Impurity

8 Extrinsic

9 Conductivity

10 Why Doping ?

11 ■ PROPERTIES OF THE MATERIALS
Silicon Polysilicon Silicon Dioxide Silicon Nitride

12 Silicon

13 Sheet Resistance

14 Polysilicon

15 Silicon Dioxide

16 Growth Speed

17 Cont’d

18 Silicon Nitride

19 Characteristics of MOS Device

20 Depletion Region

21 Current-Voltage Relations

22 ■ MOS Device Behavior

23 Basic Shape – Ids vs. Vds

24 Basic Shape –Ids vs. Vgs

25 Subthreshold Conduction

26 A model for manual analysis

27 Dynamic Behavior of MOS Transistor

28 Gate Capacitance

29 Average Gate Capacitance

30 Diffusion Capacitance

31 Junction Capacitance

32 Interface Band Structure

33 Evaluation of Vth

34 Flat-Band Voltage

35 Threshold Voltage Vth

36 Regions

37 Saturation Region

38 Cont’d

39 Id - Body Effect

40 Pinch-Off

41 Channel Length Modulation

42 Id – Channel length modulation

43 Conductance

44 Transconductance

45 Cont’d

46 Cont’d

47 Avalanche Region

48 Avalanche

49 gds

50 MOS Scaling

51 Parameter Variation

52 Variations

53 Process Corners

54 Corners

55 Library

56 What to Look for

57 Style, cont’d

58 Some Struggle

59 ■ Sub-Micron MOS Transistor
Threshold Variations • Parasitic Resistances • Velocity Sauturation and Mobility Degradation • Subthreshold Conduction • Latchup

60 Technology Evolution

61 SPICE MODELS Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular

62 MAIN MOS SPICE PARAMETERS

63 SPICE Parameters for Parasitics

64 Technology Evolution

65 Process Variations Devices parameters vary between runs and even on
the same die! Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices.

66 Impact of Device Variations

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