Introduction to Quartus and the APEX 20K Device Family

Introduction to Quartus and the APEX 20K Device Family

Class Goals Learn about the capabilities in Quartus
Learn to use different design entry techniques Design entry methods available within Quartus Text editor Block diagram/schematic file editor Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic Learn how to manage a design project Setting up a project Compiling a project

Class Goals Learn about verification using other EDA Tools
Interfacing with simulators and timing analyzers from Cadence, Model Technology, Synopsys, and Viewlogic Introduction to APEX 20K and APEX 20KE devices APEX 20K architectural features Carry Chain and Cascade Chain

Agenda Introduction to Altera & Altera Devices
Introduction to the Quartus development system Quartus design environment Quartus design methodology Design Entry Setting up the Project Compilation Introduction to APEX 20K and APEX 20KE Architectural features Carry Chain and Cascade Chain Review and Support The agenda for the Design Entry training section is: First, we will go over some common design methodologies that are used by designers and how Quartus fits in that flow. Then we will cover the new design entry tool - block/schematic editor. Followed by a review of LPMs, MegaWizard Plug-in Manager and Text editor for HDLs which are similar to Quartus. Quartus has another new design entry tool - the memory editor which can be used to create memory initialization files, and finally we look at the netlist-support from 3rd party EDA companies. We will work on a example design to go over some of the topics discussed here.

Introduction to Altera & Altera Devices

Introduction to Altera
An industry leader in programmable logic Inventor of the EPLD in 1983 Eight programmable logic families Look-up table-based and Product term-based APEX 20K Look-up table-based FLEX 6000, FLEX 8000, FLEX 10K Product term-based Classic, MAX 5000, MAX 7000, MAX 9000 Software development systems: Quartus, MAX+PLUS II

Introduction to the Quartus Development System

Quartus Development System
Quartus Development System contains a wealth of features: Fully integrated design entry, processing, and verification tools: Multiple design entry methods Logic synthesis Place & route Simulation Timing analysis Device programming Advanced EDA tool integration Workgroup computing Support for Intellectual Property (IP) functions System-level verification of devices running at system speed

More Features Incremental Recompilation
Internet-enabled technical support Supports multiple platforms1 Quartus runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations Extensive on-line help Network licensing supported on both Windows-based PCs and Unix-based workstations Note 1: Please refer to Quartus’ ReadMe file to determine which version of the Operating System is supported for each platform

More Features Verilog HDL Testbench VHDL Testbench
Multi-processor support Computer-intensive functions are distributed to multiple processors locally and/or across operating systems to reduce compilation times On-line help in Japanese

Advanced EDA Tool Integration
Altera works closely with EDA partners to develop a truly seamless interface between the Quartus and EDA tools NativeLink integration NativeLink integration enables users to launch and control Quartus from other EDA tools Minimizes the need to learn new design tools Parameters can be passed efficiently between EDA tools and Quartus, enabling designers to effectively debug their designs in the EDA tool Traditional interfaces through EDIF 200 and 300, LPM 2.20, SDF 1.0 and 2.0, VITAL 95, Verilog HDL, and VHDL 1987 and 1993 are also supported

Workgroup Computing Multiple designers can work on a single project using global file management and design revision control Revision Control software supported PVCS SCCS RCS Designers can create a custom Tcl script to carry out this interface

Intellectual Property (IP) Support
MegaCore Program Staffed with Altera employees MegaCore group develops functions that support the PCI bus interface, DSP applications, and communication applications AMPP Program (Altera Megafunction Partners Program) AMPP partners are 3rd party IP developers who design IP optimized for Altera devices Both programs support OpenCore which allows designers to evaluate megafunctions prior to licensing

System-Level Verification
SignalTap logic analyzer offers system-level verification of devices running at speed Verification times are reduced Megafunction provided free of charge with Quartus SignalTap works together with Quartus and the MasterBlaster communication cable

Internet-Enabled Support
Software updates License file delivery Submit service requests directly to Altera Applications and monitor the progress on-line Browse your service requests to ascertain their status and resolution Quartus generates some messages with embedded URLs to enable designers to locate relevant material from Altera’s web site

Internet Capabilities
Launch web browser window from within Quartus View > Auxiliary Windows > Web Browser

Quartus Design Environment

Quartus Operating Environment
Project Navigator Window Status Window Messages Window

Questions about Quartus?
Quartus on-line Help has the answers Contains the complete up-to-date information on Quartus Provides tips on how to effectively work with Quartus tools Provides answers and examples To access on-line Help Help menu content: Starting Projects Creating and editing files Using AHDL, VHDL, Verilog Libraries: logic functions, Megafunctons, Primitives Using other EDA tools Programming or configuring a device Press F1 or Shift-F1 to access context sensitive help

Quartus Design Methodology

Design Entry Design Specification System Production
Design Modification Design Compilation Functional Verification Command-Line Mode: Scripting Timing Verification Device Programming In-System Verification System Production

Design Methodologies Quartus supports three common design methodologies: Top-down Create a top-level of the design first, and then break down the design into lower-level design blocks. Bottom-up Begin by creating the lower-level design blocks first and then stitch together the design at the top-level. Middle-out Start in-between Top-down and Bottom-up design methodologies There are three design methodologies commonly used by designers. First one is top-down where you begin by just creating a top-level drawing of the design. Then you break it down into smaller blocks which can be the lower-level modules. In the bottom-up design approach, the designer defines all the small blocks of the design. Once all the lower blocks are created, they are stitched together to create the complete design. And then there is the middle-out approach. Quartus fits into all of these design methodologies and makes it easy to design whatever your style.

Design Entry Multiple design entry methods Quartus
Block/Schematic Editor Text Editor AHDL, VHDL, Verilog Memory Editor Hex, Mif Third party EDA tools EDIF HDL VQM Add flexibility and optimization to the design entry process by: Mixing and matching design files Using LPM and Megafunctions to accelerate design entry There are multiple methods of entering designs in Quartus - using either the block/schematic editor, text editor, memory editor or importing netlists from 3rd party EDA tools. The use of LPMs and Megafunctions greatly improves the flexibility, and speeds up the design entry process. You can also mix and match different source files in the project.

Design Entry Files Verilog VHDL Exemplar, Synopsys, Synplicity, etc...
Quartus Block Editor Quartus Text Editor Quartus Memory Editor Verilog MegaWizard Manager VHDL Exemplar, Synopsys, Synplicity, etc... Top-Level File Top-level design files can be .bdf, .tdf, .vhd, .vhdl, .v, .vlg, .edif or .edf AHDL Schematic Schematic .bdf .gdf .bsf .tdf .vhd .v Text File .edf .edif .v, .vlg, .vhd, .vhdl, vqm This figure shows all the design source files supported by Quartus. The schematic files are .bdf, .bsf and .gdf. BDF is the block design file, BSF is the block symbol file and support of GDF file is for backward-compatibility with Quartus. The text files are VHDL, Verilog and AHDL (.tdf) Or you can import netlist files in EDIF or HDL format. Note that the file extensions for HDL need not be .v or .vhd only. Block File Symbol File Text File Text File Text File Text File Generated within Quartus Imported from third-party EDA tools

Resource Libraries The following libraries are added to the project by default LPM Library of Parameterized Modules ( LPMs ) Industry standard logic functions LPM_ADD_SUB, LPM_COUNTER, etc. Others 7400 series logic functions (to provide support for older designs) Other legacy functions like 161mux, 8fadd, etc. Primitives Basic logic building blocks When you create a project, the following resource libraries are automatically added to the project: The primitives library that contains all the basic logic building blocks like AND, NOR, etc. Under the others directory it contain libraries for 7400 logic family and macrofunctions such as 161mux, 8fadd, etc. It also adds all the LPM functions and megafunctions like busmux and divide. The VHDL 1987 and 1993 library elements are added too.

Add User Libraries Menu Bar: Project > General Setting...
Step 1: Select User Libraries Step 2: Select Library path Step 3: Click Add Step 4: Click OK Adding User Libraries can also be done using Project Wizard. Refer to the section on Project Wizard for more information You add user libraries to the project during the Project setup. On page 2 of the project setup page, click the User Library Pathnames button which opens a new window. Add the user libraries.

Text Design Entry Available Features Enter text description
Line numbering in the HDL text files Preview of HDL templates Syntax Coloring When editing a text file, an asterisk (*) appears next to the filename After saving the file, the asterisk disappears Enter text description AHDL (.tdf) VHDL (.vhd) Verilog (.v)

HDL Templates Select HDL language. Select Template section. Preview window display section Menu Bar: Insert > Template… or click on the shortcut button

Edit Options Upper Left-hand Corner of the Screen Increase Indent
Decrease Indent Find Matching Delimiter Upper Left-hand Corner of the Screen

Text Editor: Options Menu Bar: Tools > Options...

AHDL Altera Hardware Description Language
High-level hardware behavior description language Uses Boolean equations, arithmetic operators, truth tables, conditional statements, etc. Can create AHDL Design File (.tdf) with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has AHDL templates and syntax coloring

Learn more about Verilog in Altera Verilog Customer Training Classes
1993 Verilog IEEE 1364 standard Hardware Description Language Can create Verilog design files with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has Verilog templates and syntax coloring Features Tasks 2-D Arrays Empty placeholder State machine recognition Verilog TestBench support Coming Soon: Verilog Testbench Learn more about Verilog in Altera Verilog Customer Training Classes

Learn more about VHDL in Altera VHDL Customer Training Classes
VHSIC Hardware Description Language 1987 and 1993 IEEE 1074 standards supported Can create VHDL design files (.vhd) with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has VHDL Templates and syntax coloring VHDL TestBench support Coming Soon: VHDL Testbench Learn more about VHDL in Altera VHDL Customer Training Classes

Block Diagram/Schematic File Editor
This is both a block diagram editor and a schematic file editor Block diagram entry is mainly for top-down design methodology Schematic file entry is the traditional schematic design entry User can enter blocks, primitives, LPMs, and megafunctions from Quartus-provided or user libraries Provides “smart” block connection and mapping MAX+plus II graphic design files can be imported This is a very powerful design entry tool in Quartus. It is easy to use and fits well in the top-down design methodology. In the top-down design environment, you can use block editor to draw the top-level block diagram and then break down the lower-level modules. This is how most large designs begin - rough sketches of the lower level blocks and how they will be connected. In the bottom-up design environment, once you have created the lower-level designs you can use the block editor to stitch the whole design together. The block editor has “smart” block connection and mapping features, which I will discuss in detail.

Block Editor - Entry Process
Create new block design file Draw block diagram or enter design components (symbols) Enter port and parameter information Connect components with connectors (wires and buses) Add mapping properties to connectors, if needed Save the design The file extension is .bdf Create new project (covered in Projects section) Add user libraries Generate HDL/graphic file for the lower-level blocks Create symbol or include file of the top-level block design The steps involved in creating a block diagram are as follows: You begin by creating a new project. During this step you should add any user libraries that you may want to use. This was covered in the Projects section. Then you create a new block design file - draw the block diagrams, enter symbols or LPMs, and enter port information for the blocks. Once you have all the blocks drawn, connect them using connectors - either buses or wires. It may be necessary to assign properties to the connectors. Save the design with .bdf extension. Now, you can generate HDL/graphic file templates for the lower-level blocks. Or create a symbol file of the whole top-level block design, which can be used in bottom-up design environment.

Block Editor - Create New File
Create a block/schematic file Menu Bar: File > New > Block/Schematic document Open new file Select Block/Schematic Document To create a new file, from the File menu select New. Then select Block/schematic document

Block Editor - Draw Block Diagram
Create block diagram using the toolbar and enter ports Click on the toolbar option “Block” to draw a block diagram Block A Right-click on the block. Select Properties from the pop-up menu. Enter port information. Click on the “Block” button from the toolbar to start drawing the block diagram. To enter port information for the block, right-click on the block and choose Properties from the pop-up menu Enter information in the Block Properties dialog box such as block name and I/Os.

Block Editor - Enter Symbols
Enter symbols from libraries - LPMs, primitives, others Click on the toolbar option “Insert Symbol” OR Double-click in block editor to insert symbols Block A To enter symbols from any of the libraries, double-click in the block document. This opens the Insert Symbol dialog box. Choose the element you want to insert from the list - lpm, primitives and others. Symbol libraries Preview the Symbol

Block Editor - Enter Symbols
Enter symbols from libraries - LPMs, primitives, others Import GDF files created in MAX+plus II v9.1 and later Block A Block B Insert an LPM Insert a primitive cell Once selected place the symbols in the block diagram.

Block Editor - Make Connections
Wire (Single bit line) Bus (Multiple bits) Wire Block A Block B Bus Once you have different blocks and symbols entered, you can now connect the design. This is done by using connectors which can be either a bus or a wire.

Check Connection Right Mouse Click on the connector > Conduit Properties

Quartus has “smart” block connecting and mapping You do not have to label connectors if the I/O names between different blocks are the same One connector will connect all the common I/Os between the blocks Mapper Connector Block A Block B Quartus has “smart” block connecting and mapping features. What does this mean? Two things: You do not have to label the connectors if the I/O names you entered in the blocks are the same. So, if you have I/O dataB in inst1 and inst2, drawing a connector between these 2 blocks will automatically connect the I/O. Secondly, if there are multiple I/Os common between blocks, then you have to draw just one connector to connect all common I/Os. This happens only if the names are same among the different blocks. So, dataB, addrA, addrB and ctrl1 are connected between inst1 and inst2.

Connector Properties You have to map the block I/Os when the I/O names are different between the blocks 1 First, label the connector Select connector  right-click  choose Properties  enter Name Block A ConnectorAB Block B If the I/Os that you wish to connect have different names, then you have to explicitly do mapping. First, you label the connector. To do this, select the connector and right-click. Choose Properties option from the pop-up menu. Then enter a Name. ConnectorAB Enter Signal

Mapper Properties Double-click on the mapper
ConnectorAB Block B Block A 2 Select the mapper and double-click on it to open the Mapper Properties dialog box 3 In the General tab, set the Mapper Type - Input, Output, Bidir 4 In the Mappings tab, set the I/O on block and connector signal 5 Click Add and hit OK After labeling the connector, add mapper properties. Select the mapper and double-click on it. This opens up the Mapper Properties dialog box. From the General tab, set the mapper type - input, output or bidirectional. Then from the Mappings tab, enter the I/O on the block and connector signal. Click Add and OK.

6 Enter mapper properties on both the blocks 7 Now, the I/Os are connected Mapper Annotation Box Block A ConnectorAB Block B IIIII Enter mapper properties on both the blocks. Now the I/O are connected.

Block Editor - Save Design
Save the design file with .bdf extension Block A ConnectorAB Block B Once you have entered all the information, save the design as a .bdf file Design File Name

Block Editor - Generate Design File
Create HDL or graphic design file for individual blocks Block A Block B ConnectorAB Right-click on the symbol to open the pop-up menu Select Create Design File from the menu Another great feature of the block editor is you can generate HDL or graphic file templates of lower-level blocks. This is specially helpful in top-down design environment. To do this, select the block and then right-click. From the pop-up menu select Create Design File.

Block Editor - Generate Design File
Choose from the File Type and enter File Name Block A Block B ConnectorAB Select from AHDL, VHDL, Verilog or Graphic option This brings up the Create Design File dialog box. Choose the HDL style or graphic option and enter a file name. This will create a template with all the port information you entered and the basic HDL structure (module, entity, or subdesign constructs).

Create Design File Quartus creates a design file that contains the port names that are specified in your block. These lines are necessary for Quartus to update the source code module myblk ( // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE! in1, in2, out1, out2 // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE! ); // Port Declaration // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! input in1; input in2; output out1; output out2; // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! endmodule

Update Design File... Before After
If you change the name or number of I/Os in your block, Quartus can update the design file for you Step 1 : Right mouse click Update Design File...

Updated Design File module myblk (
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE! in1, in2, out1, out2, out3 // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE! ); // Port Declaration // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! input in1; input in2; output out1; output out2; output out3; // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! endmodule Quartus updated the source file with the additional pin, out3

Block Editor - Generate Symbol File
Menu Bar: Tools > Create symbol for current file Creates .bsf file Block A ConnectorAB Block B IIIII After saving the file you can create a symbol file of the whole design. Do this by selecting Create Symbol File option from the File menu. The symbol file can then be used if you are using a bottom-up design approach.

Block Editor - Generate Include File
Menu Bar: Tools > Create Include file for current file Creates .inc file Block A ConnectorAB Block B IIIII You can also create an include file of the block design file. This is similar to Quartus, where an AHDL file references the include file. To create the include file select Create Include File option from the File menu.

Block Editor - Options Menu Bar: Tools > Options
Change the preferences of the Block/schematic editor, by selecting Preferences option from the Tools menu. From this page you can control grid options, hide/display annotation boxes.

Memory Editor Create or edit memory files in hex format (.hex) or memory initialization format (.mif) For Design Entry If you have a memory block in your design (ex. RAM, ROM, or Dual-port RAM), you can use the memory editor to create a memory initialization file to initialize your memory block For Simulation You can create an initialization file to initialize your memory during simulation Another new design entry tool in Quartus is the memory editor. You can use this editor to create memory initialization files in both the hex and mif format. These are used to initialize the ROM and to initialize memory during simulation.

Memory Editor - Create New File
Create memory file Menu Bar: File > New > Other Files tab Hex Document Mif Document To create a new memory file, From the file menu select New and then choose either the Hex document or the Mif document from the New dialog box.

Create memory file Enter Number of Words and Word Size The memory editor asks for the Number of Words and the Word Size to create the file. Enter the appropriate information.

Opens memory editor window with the required number of words and word size Words OR Cells Quartus then opens the memory editor with the entered Number of Words and the Word Size.

Memory Editor - Options
Changing memory editor options View  Select from available options Show ASCII Equivalents Cell Per Row You can change some of the options in the memory editor. The option Cell per Row varies the number cells in a row between 1, 2, 4, 8, 16, 32 and Auto. The file on the right has 8 cells per row.

Memory Editor - Options
Changing radix settings of memory editor View  Address/Memory Radix Address Radix Memory Radix You can also change the radix of the address and memory - binary, decimal, hex or octal. Additionally, for the memory, decimal can be signed or unsigned.

Memory Editor - Edit Contents
Create memory file Edit contents of the memory file Select the word and type in a value OR Select the word and right click to select an option from the pop-up menu Now you can start editing the contents of the memory file by selecting the word and entering in new values. You can do this by directly typing in the values or by right-clicking on the word and using options from the pop-up menu.

Memory Editor - Save File
Create memory file Save the memory file as .hex or .mif file . Once you have entered all the information, save the file as .hex or .mif.

EDA Interfaces Introduction
Quartus can interface with industry-standard EDA tools that generate an EDIF 200 netlist file, a VHDL 1987 netlist file, VHDL 1993 netlist file, or a Verilog HDL netlist file NativeLink interface provides truly seamless integration with third-party EDA software tools EDA tools can automatically run Quartus and transfer information to and from Quartus in the background Designers can complete entire designs without “leaving” their tools Vendor Driven Flow

Introduction to Quartus Design Flows
Quartus allows for three possible design flows : Quartus Driven Flow: User launches other EDA tools from Quartus No need to learn 3rd party EDA tool Vendor Driven Flow: User runs Quartus in the background from the 3rd party EDA tools File Based Flow: Very little integration between Quartus and 3rd party EDA tools

Third party EDA software drives Quartus
Vendor Driven Flow Third party EDA software drives Quartus Offers the tightest code-level integration between tools Quartus appears ‘Native’ in third party EDA software Synthesis Tool Cross Probe Error Locate API Tcl COM (C++, VBScript)

Quartus drives the third party EDA software
Quartus Driven Flow EDA tools launched from within Quartus Code level integration Cross probing and error location Quartus automatically generates the netlists or reads in the netlists based on the tool User doesn’t have to learn the setup and the flow Quartus drives the third party EDA software Cross Probe Error Locate API Tcl COM (C++, VBScript) Synthesis Tool

NativeLink Features Minimizes designer interaction with different EDA tools Allows designers to complete their designs using as little as one tool Cross-referencing Nodes from place-and-route result can be traced back to HDL code across from Quartus to a synthesis tool Improved Quality of Results (QoR) Nativelink lets synthesis tools map directly into the fundamental building block of an architecture Iterative Compile Improves QoR from synthesis tools Allows Quartus to pass routing delay information after place-and-route back to the synthesis tools Synthesis tools can then re-synthesize the design based on the feedback

Tools Supported by Quartus
Synthesis Tools Design Compiler FPGA Express FPGA Compiler II Leonardo Spectrum Synplify Design Entry: View Draw Simulation Tools ModelSim VCS/VCSI VSS Verilog-XL Speed Wave Timing Analyzers: Motive Primetime 1 1 1 Note 1: These synthesis tools support iterative compile capability

NativeLink Quartus NativeLink interface is comprised of two components: External Files: WYSIWYG (What You See Is What You Get) ATOM netlist files (EDIF, Verilog, VHDL) cross reference files (ex. xrf), timing files (ex. sdo) etc. Application Programming Interface (API) Functions - a pre-defined interface API Quartus EDA Partners External Files

WYSIWYG ATOM Primitives
A set of design primitives that support WYSIWYG compilation Provides direct control of how a design is technology mapped to a specific target device Helps synthesis vendors provide an optimal realization of a design for a device architecture WYSIWYG elements in the design are translated as directly as possible for fitting and routing purposes

WYSIWYG Compilation Flow
EDA Synthesis Partner Place & Route Netlist Extraction Database Builder Synthesis EDIF Verilog VHDL QUARTUS Design Input Files with WYSIWYG Primitives

Iterative Compilation Flow
Area & Timing Constraints SYNTHESIS TOOL ATOM Netlist EDIF VHDL Verilog Device Database & Delay Annotator C O M P I L E R SDF File Partial Placement Good Timing Estimation Final Placement Better Timing Estimation Routing QUARTUS Best Timing Estimation

Project > EDA Tool Settings...
Quartus Driven Flow Project > EDA Tool Settings... ATOM netlist is automatically generated when you choose a NativeLink EDA Tool The correct data format is automatically chosen Quartus Driven Flow

EDA Driven Flow Run Quartus in the background: Background Compile

File Based Flow: Non-NativeLink
If a non-NativeLink EDA Tool generates a VHDL, Verilog, EDIF file, then specify a .lmf for that file format Can be EDIF, VHDL, or Verilog Select a library mapping file (lmf) Project > EDA Tool Settings... Select Custom Select Settings...

Summary Synthesis: Verification: Mentor Graphics Leonardo Spectrum
Synopsys Design Compiler Synopsys FPGA Express Synplicity Synplify Verification: Cadence Verilog-XL Model Technology ModelSim Synopsys PrimeTime Synopsys Motive

Quartus Projects

Project Definitions Quartus Project:
A collection of related design files and libraries Must have at least one designated top level entity Targets a single device or can be partitioned into multiple devices Stores project settings in Project Settings File (.PSF)

Agenda New Project Wizard Project Menu Project Settings File (.PSF)
Quick way to create a new project Easy way to import an existing MAX+PLUS II project Project Menu Edit existing project settings Non-Wizard settings Project Settings File (.PSF) Project Navigator

Creating a New Project 1. Invoke New Project Wizard
2. Select Working directory 3. Name of Project. Recommendation: Use top- level design entity

Creating a New Project 4. Add design files
- Graphic (.BDF, .GDF) - AHDL - VHDL - Verilog - EDIF Notes: All files in the project directory do not need to be added Add top level file if file name and entity name are not the same 5. Add user library pathnames and files

Creating a New Project 5(cont.) Add user library pathnames and files
User Libraries (ex. MegaWizard functions) MegaCores/AMPP libraries Pre-compiled VHDL packages Browse to file and click on Add.

Creating a New Project 6. Review results and click on Finish

New Project (Completed)
Project Name & Directory

MAX+PLUS II to Quartus Converting MAX+PLUS II designs to Quartus:
Browse to project directory Set top level file/entity No need to add other files in directory Add: Any files not located in same directory Any user directories as libraries Notes - Any Graphic Design File (.GDF) from MAX+PLUS II that is edited within Quartus can only be saved as a Block Diagram File (.BDF) by Quartus - Symbols with .GDF files may have to be updated - The Assignment & Configuration File (.ACF) from MAX+PLUS II is not recognized by Quartus

Project Menu Edit the settings for an existing project
Adding/removing files or libraries Non-Wizard project settings HDL interface Third Party EDA Flow Other settings discussed later Timing Revision Control Note: All Project settings except project name and top level entity default to the settings of the previously opened project

Editing Project Settings
Existing project must first be opened to edit the settings Open the Existing Project

Access via the General Settings dialog box To add/remove project files Adding - Browse to file - Click Add Removing - Select file from list - Click Remove

To add/remove project libraries Adding - Browse to directory - Click Add Removing - Select library from list - Click Remove

VHDL Input Files Select VHDL version
Enter Library names when directly compiling VHDL files with Quartus that contain user-created packages If gate level VHDL netlist file is used, specify mapping file (discussed later)

Verilog Input Files If gate level Verilog netlist file is used, specify mapping file (discussed later)

Project Settings File (PSF)
Stores all project setting information Automatically generated by Quartus Quartus default file name is <project_name.psf> Can be manually edited inside Quartus

Sample Project Settings File (PSF)
DEFAULT_LOGIC_OPTIONS { DUPLICATE_LOGIC_EXTRACTION = ON; AUTO_TURBO_BIT = ON; AUTO_OPEN_DRAIN_PINS = ON; AUTO_PARALLEL_EXPANDERS = ON; AUTO_OUTPUT_REGISTERS = OFF; AUTO_INPUT_REGISTERS = OFF; AUTO_DELAY_CHAINS = ON; AUTO_CASCADE_CHAINS = ON; AUTO_CARRY_CHAINS = ON; PARALLEL_EXPANDER_CHAIN_LENGTH = 16; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN_LENGTH = 32; NOT_GATE_PUSH_BACK = ON; SLOW_SLEW_RATE = OFF; STATE_MACHINE_PROCESSING = AUTO; } DEFAULT_TIMING_REQUIREMENTS IGNORE_REQUIREMENTS_FOR_FITTER = ON; CUT_OFF_IO_PIN_FEEDBACK = ON; CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; CUT_OFF_READ_DURING_WRITE_PATH = ON; PROJECT_INFO(test) THIRD_PARTY_EDA_TOOLS(test) Default Logic Options (partial listing) Timing Analysis Information EDA Tool Information

Project Navigator Graphical display used to study project relationships Active in both Compilation and Simulation modes Three views Hierarchies view Files view Design Units view

Views of the Project Navigator
Hierarchy View Displays Project Hierarchy after project is analyzed Can be used to make assignments

Files View Shows all files in the project All source files appear under Design Files Simulation files, include files, etc., appear under Other Files

Design Unit view Displays each design unit a design entity that can be used together with gates, registers, and megafunctions in a design file Displays type, e.g. AHDL entity Details the File in which it is instantiated Design Unit Associated Design File

Project Summary Use Project Wizard to create new projects
Use Project Menu dialog boxes to Edit existing project settings Set up Third Party interface Use Project Navigator to study file and entity relationships within the project

Please go to Laboratory Exercise Manual,

Quartus Compilation

Agenda Compiler Settings and Focus Points Compiler Settings Wizard
Introduction Compiler Settings Wizard Compilation Steps Compiler Settings Menu Edit existing compiler settings Non-Wizard settings Compiler Settings File (.CSF) Compiler Report Summary

What are Compiler Settings?
Compiler control information Device Pin assignments Level of compilation Point of compilation in hierarchy Synthesis & fitting Verification Accessed via the Processing Menu Each contains a focus point (next slide) Information stored in a Compiler Settings File (.CSF)

What are Focus Points? Design entities
Points for compilation in a hierarchy Entity is compiled as if it were the top level Top-level entity is the default focus point Focus Point A B C D E Focus Point F

Benefit of Compiler Settings
Designers can work on sub-modules within a project without changing top level settings Can obtain fit & performance information for that particular entity Incomplete designs A Focus Point B C D Modules B, E, & F can be compiled even though Modules C & D are incomplete E F

Focus Points Hierarchy View
Displays Project Hierarchy after project is analyzed Can be used to set and view focus points Shows design entity is a project focus point Shows design entity is the current project focus point

Compiler Settings Wizard (Steps 1, 2 & 3)
Use to browse through hierarchy tree 1. Invoke Compiler Settings Wizard 2. Select focus point 3. Select compiler settings name Note: Quartus defaults to <hierarchyname_entityname>

Compiler Settings Wizard (Steps 4 & 5)
4. Select compilation level - Netlist extraction only - Full compilation 5. Select Normal Compilation versus Smart Compilation Note: Must use Smart Compilation for incremental re-compilation.

Compilation Definitions
Compilation Types Netlist extraction and synthesis only Compiler synthesizes gate-level code from design files Compiler stops after synthesis Compiler will generate estimated timing values only Full compilation, including netlist extraction, synthesis, and fitting Compiler performs the above and fits the design into a device Compiler will generate actual timing values from device data and programming files

Compilation Definitions
Compilation Speed vs Disk Space Normal compilation The Compiler will re-extract netlists only from design files that have changed Compilation uses less disk space but takes more time Smart compilation The Compiler will save extra data in order to speed up future re-compilations Compilation takes less time but uses more disk space

Compiler Settings Wizard (Step 6)
6. Do you want to assign a device? Note: Selecting “No” will turn on ‘Auto’ device selection which will choose the smallest device needed to achieve a fit

Compiler Settings Wizard (Step 7a)
7a. If no device selected, use filters to narrow the devices from which the compiler will choose OR

Compiler Settings Wizard (Step 7b)
7b. Select device and use filters to narrow the devices displayed

Compiler Settings Wizard (Step 8 & 9)
8. Run timing analysis after compilation? 9. Run simulation after compilation? Note: This allows a user to initiate a simulation using the previously stored Simulator Settings selected

Compiler Settings Wizard (Summary)
10. Review results and click on Finish.

Compiling in Quartus (Start)
1 Perform Analysis & Elaboration (Save & Check) - Compilation stops after file is analyzed for syntax errors Perform Full Compilation (based on all compiler settings)

Compiling in Quartus 2 Status Bar Compiler Messages

Done! 3 The Compiler Report Note:
Quartus automatically opens Compiler Report when compilation is started

Compiler Settings Menu
Edit existing compiler settings Change device Change compilation level Add/remove automatic timing analysis or batch simulation Turn on/off Timing Driven Compilation Non-Wizard compiler settings Pin assignments Timing-driven compilation

Editing Compiler Settings
Select Compiler Setting from drop-down menu All available Compiler Settings with related focus points

Editing Compiler Settings
Specify New Device Make Pin Assignments

Compiler Settings - Pin Assignments
1. Select a pin number 2. Invoke Node Finder to find pin name or type 3. Add to assignment list

Compiler Settings - Timing Driven Compilation
Directs the compiler to synthesize & place logic to meet specified timing requirements Default is ON (option enabled)

Compiler Settings File (.CSF)
Stores compiler options for a particular module/entity Default file name is <hierarchy_levels_focus_point>.csf Automatically created for top level entity Can be manually edited in Quartus New .CSF copies settings from previous .CSF Focus Point = modulea.csf A B C D E Focus Point F = modulea_moduleb_modulef.csf

Sample Compiler Settings File (.CSF)
{ FOCUS_ENTITY_NAME = |rfifo; RUN_TIMING_ANALYSES = ON; FAMILY = APEX20K; USE_TIMING_DRIVEN_COMPILATION = OFF; COMPILATION_LEVEL = FULL; SAVE_DISK_SPACE = ON; SPEED_DISK_USAGE_TRADEOFF = NORMAL; } CHIP(rfifo) DEVICE = "EP20K100TC144-3"; AUTO_RESTART_CONFIGURATION = OFF; RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; USER_START_UP_CLOCK = OFF; ENABLE_DEVICE_WIDE_RESET = OFF; ENABLE_DEVICE_WIDE_OE = OFF; ENABLE_INIT_DONE_OUTPUT = OFF; ENABLE_LOCK_OUTPUT = OFF; JTAG_USER_CODE = 0XFFFFFFFF; CONFIGURATION_SCHEME = "PASSIVE SERIAL"; USE_CONFIGURATION_DEVICE_OPTIONS = OFF; USE_CONFIGURATION_DEVICE_NAME = EPC2LC20; CONFIGURATION_DEVICE_USER_JTAG_CODE = 0XFFFFFFFF; AUTO_INCREMENT_USER_JTAG_CODE = ON; DISABLE_CONF_DONE_AND_NSTATUS_ON_EPROM = OFF; GENERATE_TTF_FILE = OFF; GENERATE_RBF_FILE = OFF; GENERATE_HEX_FILE = OFF; HEX_FILE_START_ADDRESS = 0; HEX_FILE_COUNT_UP_DOWN = UP; RESERVED_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; NWS_NRS_NCS_CS_RESERVED = OFF; RDYNBUSY_RESERVED = OFF; DATA7_1_RESERVED = OFF; |aclr : LOCATION = PIN_10; Compiler Control Settings Device & Device Options

Controlling Synthesis & Fitting
Assignments are used to control logic synthesis and place & route operations Assignments are generally made after the initial compilation to resolve fit or performance issues Examples of assignments are: Pin Assignments Synthesis Logic Options Timing Requirements Clique Assignments stored in Entity Settings File (.ESF)

Adding Assignments Invoke the Assignment Organizer by highlighting an entity in the Hierarchy View and right clicking OR From the Tools Menu

Assignment Organizer Edit default logic options for project (stored in .PSF) Add assignments to a specific entity and node Launches Node Finder

Node Finder 1. Select entity in which to search for nodes
List of nodes in selected entity & lower levels of hierarchy 2. Use Filter to select the nodes to be displayed Note: Can create & save custom filter (next slide)

Node Finder 5. Click OK when all nodes are selected 3. Start Search
4. Highlight node(s) and use arrow keys select/deselect

Creating a Custom Filter
1. Select Customize 2. Click New. Name Filter and click OK. 3. Select Filter settings

Assignment Organizer 3 types of Logic Options
- Options for Individual Nodes Only - Options for Nodes and Entities - Options for Entities Only 3. Click Add to add assignment 1. Click to add new assignment 2. Choose assignment and setting

Assignment Organizer Store in assignments for: “This instance only”
Stores assignment in the top-level .ESF Assignment made to only the selected instance “This instance in all occurrences of its parent entity” Stores assignment in the .ESF for the entity one hierarchical level up Assignment applied to all instances under that level “All instances of this entity” Stores assignment in a separate entity settings file for that entity Assignment applied to all instances in project

Assignment Organizer A B C D D D Store in assignments for:
“This instance only” Stores assignment in the top-level .ESF Assignment made to only the selected instance “This instance in all occurrences of its parent entity” Stores assignment in the .ESF for the entity one hierarchical level up Assignment applied to all instances under that level “All instances of this entity” Stores assignment in a separate entity settings file for that entity Assignment applied to all instances in project A B C D D D

Assignment Organizer By Category tab sorts all assignments and shows the file in which the assignment is stored

Options for Individual Nodes Only
These are assignments which you want to apply on an individual basis to improve the performance on a critical path Individual Logic Options & Defaults GLOBAL SIGNAL = OFF FAST INPUT REGISTER = OFF FAST OUTPUT REGISTER = OFF CLOCK ENABLE ROUTING = PERIPHERAL OUTPUT ENABLE ROUTING = PERIPHERAL CLKLOCKX1 INPUT FREQUENCY IMPLEMENT AS OUTPUT OF LOGIC_CELL = OFF DECREASE INPUT DELAY TO INTERNAL CELLS = OFF

Options for Nodes and Entities
These are options which tend to be applied to a group of nodes Every node in the selected hierarchy can be selected, or Select the nodes individually if hierarchy is insufficient Logic Options & Defaults STATE MACHINE PROCESSING = AUTO SLOW SLEW RATE = OFF POWER UP HIGH = OFF NOT GATE PUSH BACK = OFF PCI IO = OFF DELAY CHAIN = OFF DUPLICATE REGISTER EXTRACTION = OFF IGNORE CARRY BUFFERS = OFF IGNORE CASCADE BUFFERS = OFF IGNORE GLOBAL BUFFERS = OFF IGNORE SOFT BUFFERS = OFF TURBO BIT = OFF

STATE MACHINE PROCESSING
Encoding is on a machine by machine basis Each machine in the user’s design can be marked with one of the following logic options: Auto: (Default) Use predetermined algorithm that is best for Family Minimal Bits: The Compiler will force the minimum number of registers to encode the machine: No. of bits = LOG2(states) (Current MAX+plus II MAX algorithm) One-Hot: The Compiler will force a one-hot encoding for the machine. (Current MAX+plus II FLEX algorithm) User-Encoded: Use the user encoding if it is enough to decode the machine otherwise use auto encoding This options are not affected by the Pterm/LUT synthesis option What is this suppose to mean? Use the user encoding if it is enough to decode the machine otherwise use auto encoding.

Options for Entities Only
Options which are applied to an entity and its children Hierarchical Options & Defaults AUTOMATIC GLOBAL = OFF AUTOMATIC GLOBAL CLOCK = OFF AUTOMATIC GLOBAL OUTPUT ENABLE = OFF AUTOMATIC GLOBAL REGISTER CONTROLS = OFF AUTOMATIC GLOBAL MEMORY CONTROLS = OFF AUTOMATIC IMPLEMENT IN ROM = OFF TECHNOLOGY MAPPER = AUTO OPTIMIZATION TECHNIQUE = AREA PRESERVE HIERARCHICAL BOUNDARY = FIRM AUTOMATIC TURBO BIT = OFF ALLOW XOR GATE USEAGE = OFF CARRY CHAIN LENGTH CASCADE CHAIN LENGTH AUTOMATIC CASCADE = OFF AUTOMATIC CARRY = OFF AUTOMATIC DELAY CHAINS = OFF AUTOMATIC INPUT REGISTERS = OFF AUTOMATIC OUTPUT REGISTERS = OFF AUTOMATIC PARALLEL EXPANDERS = OFF AUTOMATIC OPEN DRAIN PINS = OFF PARALLEL EXPANDER CHAIN LENGTH

TECHNOLOGY MAPPER Specifies which Technology Mapper to use:
LUT PTERM AUTO (PTERM or LUT) Best implementation of either PTERMS or LUT for performance Works on entire hierarchy User can choose a level if that hierarchy level and all its children will be mapped to PTERM, or LUT Recommended to use for small hierarchies only Default value is AUTO

Implementing Product-Term Logic
Logic is chosen on a hierarchical level to map to logic in product-term, LUT, or AUTO (Pterm or LUT) mode. = AUTO Hierarchical Design = Pterm Top Level = LUT AUTO assignment Pterm assignment LUT assignment Default technology mapper is LUT based User can choose on a hierarchy level if this hierarchy level and all its children will be mapped to ESB ROM, PTERM, or LUT. User can tag a hierarchy as AUTO and the best mapping is chosen for that hierarchy after that hierarchy and all its children are flattened. The mapping will be homogeneous which means all cells below that hierarchy will be using the same mode. AUTO will chose to minimize area based on a ratio of pterm/LUT. Note: This option is not useful when placed on the top level design or large hierarchies.

Technology Mapper Entity to which option applies Entity only option
Logic Option Value Assignments to which it applies

Implementing Product-Term Mode With Quartus
An entity in a design can be tagged so every instantiation of it in the design will be implemented in the same mode Stored in Assignments Hierarchical Design Top Level E = Entity tagged for Pterm Mode Pterm assignment E E E E

Making Device Assignment
Select Device from Compiler Settings Specific device Automatic Select device Family Automatic device selection Specific device selection

Entity Settings File (.ESF)
Stores synthesis and fitting assignments for nodes and entities File name is <entity_name>.esf Only created by Quartus if assignments are made Cannot be manually edited

Sample Entity Settings File (.ESF)
OPTIONS_FOR_INDIVIDUAL_NODES_ONLY { |datain[0] : FAST_INPUT_REGISTER = ON; |datain[1] : FAST_INPUT_REGISTER = ON; |datain[2] : FAST_INPUT_REGISTER = ON; |datain[3] : FAST_INPUT_REGISTER = ON; |datain[4] : FAST_INPUT_REGISTER = ON; |datain[5] : FAST_INPUT_REGISTER = ON; |datain[6] : FAST_INPUT_REGISTER = ON; |datain[7] : FAST_INPUT_REGISTER = ON; } OPTIONS_FOR_ENTITIES_ONLY { OPTIMIZATION_TECHNIQUE = SPEED; }

Compilation Summary Use Compiler Wizard to create new Compiler Settings Use Compiler Settings dialog boxes to change existing compiler settings & make pin assignments Use Compiler Report to study design implementation and resource usage Use Assignment Organizer to assign logic options

The Compiler Report Contains all information on how a design was implemented in the targeted device Device Summary Statistics Compiler Settings Floorplan Views Device Resources Used State Machines Implemented Equations Timing Analysis Results CPU Resources This a read-only window

Sample Compiler Report
Device Options

Sample Compiler Report
Device Resources Used I/O Pins Global Signals Memory Interconnect Usage Fan-Out

Reporting Timing Results
Timing information is part of the Compilation Report Summary Timing Analyses fmax (not incl. delays to/from pins) or fmax (incl. delays to/from pins) tsu (Input Setup Times) th (Input Hold Times) tco (Clock to Out Delays) tpd (Pin to Pin Delays) All timing results are reported here Reiterate that there’s no need to run the timing analyzer.

fmax Analysis fmax values are listed in ascending order. The worst fmax is listed on the top. Right mouse click, select List Paths Select fmax

Setup Time Analysis tsu = data delay - clock delay + intrinsic tsu
Register Name Clock Name Select tsu

thold Analysis thold = clock delay - data delay + intrinsic thold
Register Name Clock Name Select th

tco Analysis clock delay + intrinsic tco + data delay = tco Clock Name
Output Pins List Paths Select tco

Introduction to APEX 20K and APEX 20KE

Advanced Programmable Element MatriX (APEX)
APEX 20K Family Overview Advanced Programmable Element MatriX (APEX) Industry’s first MultiCore Architecture Look-up table (LUT) logic Product-term logic Embedded memory Fabricated on SRAM Process 2.5-V, 0.25/0.22-Micron Process 1.8-V, 0.18-Micron Process

APEX 20K Device Features All Devices Have JTAG BST Circuitry
EP20K100E EP20K100 EF20K160E EP20K200E EP20K200 EF20K300E EP20K400E EP20K400 EP20K600E EP20K1000E Features Maximum System Gates 262,912 404,480 525,824 728,064 1,051,648 1,537,024 1,771,520 Logic Elements 4,160 6,400 8,320 11,520 16,640 24,320 38,400 Maximum RAM Bits 53,248 81,920 106,496 147,456 212,992 311,296 327,680 Maximum macrocells 416 640 832 1,152 1,664 2,432 2,560 Max. User I/O 252 316 382 408 502 624 680 All Devices Have JTAG BST Circuitry (IEEE Std Compliant) Available at No Logic Cost Refer to for Latest Packaging Information

Comparison of APEX 20K & APEX 20KE
Feature APEX 20K Devices APEX 20KE Devices MultiCore System Integration Full support Full support Hot-socketing support Full support Full support SignalTap logic analysis Full support Full support 64-Bit 66-Mhz PCI Full Compliance Full Compliance 2.5-V or 3.3-V Vccio Vccio selected for device 1.8-V, 2.5-V, or 3.3-V Vccio Vccio selected block-by-block MultiVolt I/O Clock delay reduction 2x and 4x clock multiplication Clock delay reduction N/(m x k) clock multiplication Drive ClockLock output off-chip LVDS support ClockLock support Dedicated clock and input pins Six Eight

Comparison of APEX 20K & APEX 20KE
Feature APEX 20K Devices APEX 20KE Devices I/O Standard Support 3.3-V PCI LVCMOS LVTTL 3.3-V PCI 3.3-V AGP CTT GTL+ HSTL Class I, II, and III LVCMOS LVDS (in EP20K300E and larger devices) Memory support Dual-port RAM FIFO RAM ROM CAM Dual-port RAM FIFO RAM ROM

APEX 20K and APEX 20KE Architecture & Features

Architecture & Features
Dedicated Inputs, Dedicated Clocks MegaLAB ESB (Embedded System Block) LAB (Logic Array Block) Logic Element (LE) Register Packing Carry Chain Cascade Chain IO Element (IOE) PLL Features SignalTap

Device Terminology Logic Element (LE)
In Quartus, a “Cell” or “Logic Cell” (LC) is equivalent to an APEX 20K Logic Element (LE) Logic Array Block (LAB) contains 10 LEs Embedded System Block (ESB) is a block of memory that can implement memory or logic functions MegaLAB consists of 16 LABs and one ESB (EPF20K1000E has 24 LABs and one ESB per MegaLab) FastTrack Interconnect Continuous Routing Structure of an APEX 20K Device Grouped into Row, Column, MegaLAB & LAB Local Interconnects

APEX 20K Family Block Diagram
I/O I/O I/O I/O Row Column Column Column Column I/O MegaLAB MegaLAB MegaLAB MegaLAB I/O Row I/O MegaLAB MegaLAB MegaLAB MegaLAB I/O ... ... ... ... Row I/O MegaLAB MegaLAB MegaLAB MegaLAB I/O I/O I/O I/O I/O

APEX 20K MegaLAB MegaLAB Logic Element (LE) Logic Array Block (LAB)
4-Input LUT D Flipflop Carry & Cascade Chains Logic Array Block (LAB) 10 LEs MegaLAB 16 LABs 1 Embedded System Block (ESB) MegaLAB Interconnect LE LE LE LE Embedded System Block (ESB) LE LE LE LE LE LE LAB1 LAB2 LAB16 MegaLAB

Embedded System Block Enhanced Embedded Structure Product Term RAM ROM
MegaLAB Interconnect Product Term LE Embedded System Block (ESB) RAM ROM CAM (APEX 20KE) LAB1 LAB2 LAB16

(1) APEX 20KE devices have four dedicated clocks.
Product-Term Logic in ESB (1) APEX 20KE devices have four dedicated clocks.

CAM Content Addressable Memory (CAM) Available in APEX 20KE
CAM Accelerates Fast Search Applications Functions as a Parallel Comparator Order of Magnitude Faster than RAM (Serial) Looks up Data in Memory & Outputs Addresses CAM Address Data Match Flag

LABs and Local Interconnect
To or From MegaLAB Interconnect 30 LEs in a Local Area Without Using MegaLAB Interconnect 36 Local lines per Local Interconnect Every LE Drives Adjacent Local Interconnects Every LE Driven By Adjacent Local Interconnects LE 1 LE 10 LE 1 LE 10 LE 1 LE 10 Local Interconnect Local Interconnect LAB LAB LAB

3 MegaLAB Interconnect Drivers 2 FastTrack Interconnect Drivers
APEX 20K LE Connections Each LE has FastTrack and Local Outputs FastTrack Output Drives Row, Column, MegaLAB Lines Local Output Drives Local Interconnect On Either Side of LE Row MegaLAB Column Column Local Local Local 3 MegaLAB Interconnect Drivers 2 FastTrack Interconnect Drivers LE LE

Dedicated Inputs, Clocks
4 Dedicated Inputs Drive 4 Global Control Nets that Can Drive Any LE Control Signal (Clock, Clock Enable, Syn Clear, Syn Load, Clear) Four Nets of the “Peripheral Control Bus” (Clock, Clock Enable, Clear, Output Enable) Data Any Combination of Above 4 Global Control Nets Can Also Be Driven by Internal Logic 2 (APEX 20KE has 4) Dedicated Clocks Drive 2 Global Clock Nets that Can Drive LE Clock Signals IOE Clock Signals Cannot Serve as Any Other Control Signal

LAB Control Signal Generation
Dedicated Clocks 2 or 4 (1) / 4 Global Signals / Local Interconnect Local Interconnect Local Interconnect Local Interconnect SYNCLOAD or LABCLKEN2 LABCLKENA1 LABCLR1 (2) SYNCCLR or LABCLK2 (3) LABCLK1 LABCLR2 (2) Note (1): APEX 20KE devices have four dedicated clocks Note (2): LABCLR1 and LABCLR2 signals also control asynchronous preset for LEs within the LAB Note (3): SYNCCLR signal can be generated by the local interconnect or global signals

To FastTrack Interconnect, To FastTrack Interconnect,
APEX 20K Logic Element LAB-wide Synchronous Load LAB-wide Synchronous Clear Packing Register Select To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect Carry-In Cascade-In data1 Look-Up Table (LUT) Carry Chain Synchronous Load & Clear Logic PRN CLRN Cascade Chain data2 D Q data3 data4 ENA Asynchronous Clear/Preset/ Load Logic labclr1 labclr2 Chip-Wide Reset Clock & Clock Enable Select To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect labclk1 labclk2 labclkena1 labclkena2 Carry-Out Cascade-Out

To FastTrack Interconnect,
Combinatorial Logic Packing Register Select To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect Carry-In Cascade-In data1 Look-Up Table (LUT) Carry Chain Cascade Chain data2 D data3 data4 Clock & Clock Enable Select 4-Input LUT LUTs Implement Complex Functions in 1 Level of Logic Carry-Out Cascade-Out

Sequential Logic LAB-wide Synchronous Load LAB-wide Synchronous Clear Packing Register Select To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect Synchronous Load & Clear Logic PRN CLRN D Q data3 ENA Asynchronous Clear/Preset/ Load Logic labclr1 labclr2 Chip-Wide Reset Register Controls Asynchronous CLRN Asynchronous PRN Active High ENA LAB-wide Syn Load LAB-wide Syn Clear Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2 Carry-Out Cascade-Out

Preset Emulation PRN D Q Preset For Registers That Have a Preset Signal & No Clear Signal Connected a Design Quartus Emulates Preset with “Not-Gate-Push-Back” n Preset Net Connected to CLRN Port of Register n Both Register Output & Input Inverted Inversions Are Implemented in LUTs or IOEs: No Impact on Timing or Utilization CLRN D Q Preset

Architecture Features
Controlling These Features Controls Design Performance & Utilization Register Packing Allows Using LUT & Register of Same LE Separately Carry Chain Arithmetic Functions Cascade Chain Wide Fan-in Functions Features are Controlled through Quartus

Register Packing LAB-wide Synchronous Load LAB-wide Synchronous Clear Packing Register Select To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect Carry-In Cascade-In data1 Look-Up Table (LUT) Carry Chain Synchronous Load & Clear Logic PRN CLRN Cascade Chain data2 D Q data3 data4 ENA Asynchronous Clear/Preset/ Load Logic labclr1 labclr2 Chip-Wide Reset Allows LUT & Register of a LE to Be Used Separately Can Improve Utilization Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2 Carry-Out Cascade-Out

Non-Register-Packed LE
Register Bypass Path DATA1 Look-Up Table (LUT) Carry Chain Synchronous Load & Clear Logic Cascade Chain DATA2 D Q DATA3 DATA4 To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect For Purely Combinatorial Logic, Register of an LE Is Bypassed LE Has One Output that Drives: Row and/or Column Interconnects LAB Local Interconnect Possibly All Simultaneously

Register-Packed LE Register Bypass Path To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect DATA1 Look-Up Table (LUT) Carry Chain Synchronous Load & Clear Logic Cascade Chain PRN CLRN DATA2 D Q DATA3 DATA4 ENA Register Can Have an Independent Input Input Can Be Shared with LUT LE Has Two Outputs: One from LUT, One from Register

Carry Chain LAB-wide Synchronous Load LAB-wide Synchronous Clear Packing Register Select To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect Carry-In Cascade-In data1 Look-Up Table (LUT) Carry Chain Synchronous Load & Clear Logic PRN CLRN Cascade Chain data2 D Q data3 data4 ENA Asynchronous Clear/Preset/ Load Logic labclr1 labclr2 Chip-Wide Reset Clock & Clock Enable Select To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect labclk1 labclk2 labclkena1 labclkena2 Carry-Out Cascade-Out

Logic Element Modes Logic Elements Can Operate in Three Possible Modes
Normal Arithmetic Counter Each Uses LE Resources Differently, Has Unique Advantages Quartus Automatically Configures LE Based on Design Logic & User-Controllable Features Allows for a More Dense Design Allows for Enhanced Performance

APEX 20K LE Normal Mode One LUT with Four Independent Inputs
LAB-Wide Clock Enable Note (1) Cascade-In Carry-In (2) LE-Out DATA1 DATA2 PRN LUT D Q DATA3 DATA4 LE-Out ENA CLRN Cascade Out One LUT with Four Independent Inputs Normal Mode is the Default Configuration of the LE For General Combinatorial Logic Arithmetic Functions When the Carry Chain Is Not Used Note (1): There are 2 LAB-wide clock enables per LAB Note (2): When using the carry-in, the packed register feature is unavailable

APEX 20K LE Arithmetic, Counter Modes
Using the Carry Chain Allows Quartus To Configure LEs In Arithmetic Mode Counter Mode Based on Design Logic In Arithmetic and Counter Modes, an LE Contains Two LUTs, Each with Three Inputs, at Least Two of which Are Shared LUT Carry In (Dedicated Routing Resource) Carry Out Arithmetic Result (To Interconnect)

APEX 20K LE Arithmetic Mode
LAB-Wide Clock Enable Two LAB-wide clock enables per LAB Cascade-In Carry-In LE-Out PRN DATA1 DATA2 LUT D Q ENA CLRN LUT Cascade Out Carry Out Two LUTs, Each with Same Three Shared Inputs - Carry, Data1, Data2 First LUT Generates Sum Result Second LUT Generates Carry for Next Stage of Arithmetic Function

Example: Normal & Arithmetic Modes
A + B = Y A1 B1 Y1 CARRY1 A2 B2 Y2 CARRY2

Example: Normal & Arithmetic Modes
Normal Mode Arithmetic Mode LE LE CARRY1 CARRY1 LUT LUT A1 Y1 A1 B1 Y1 B1 LUT CARRY2 (Dedicated Resource) LE CARRY1 LUT A1 CARRY2 (To Interconnect) B1 ** Change Normal Mode: Logic Uses 2 LEs Arithmetic Mode: Result & Carry Generated in 1 LE

APEX 20K LE Counter Mode Register feedback multiplexer available on LE1 only LAB-Wide Synchronous Clear (2) Two LAB-wide clock enables per LAB LAB-Wide Synchronous Load (2) LAB-Wide Clock Enable Cascade-In Carry In LE-Out DATA1 (1) DATA2 (1) PRN LUT D Q DATA3 LE-Out ENA CLRN LUT Carry Out Cascade-Out Two LUTs, Each with Three Inputs - Carry & Register Feedback Shared First LUT Generates Counter Bit. Second LUT Generates Carry. Note (1): The DATA1 and DATA2 input signals can supply clock enable, up or down control, or register feedback signals for LEs other than the second LE in a LAB Note (2): LAB-Wide synchronous clear and load affect all registers in a LAB Emphasize utilization improvement of 2 LUTs in 1 LE Emphasize performance improvement of dedicated routing - carry and register feedback Emphasize “free” counter controls of mode/architecture - synchronous clear, counter enable, synchronous load; extra controls have to be implemented in extra LUTs

Counter Mode 16-Bit Loadable Counter, Up/Down Control and Synchronous Clear Using LE Modes (Carry Chain) Can Improve Utilization, Performance Using “Free” Controls of Counter Modes Maximizes LE Efficiency EP20K100-1 Logic Used (LEs) fMAX (MHz) Without Carry Chain (Normal Mode) With Carry Chain (Counter Mode) Example of improvement when using carry chain Example of extra control logic beyond “free” controls of mode

Carry Chain Number of Chains Length of Each Chain Further Reading
A Large Number of Chains May Reduce Routability Try Turning OFF Carry Chains for Non-Speed Critical Modules Length of Each Chain In General, Maximum Length Should Be 32 LEs for Ease-Of-Fit For Ripple-Carry Longer Than 32 LEs, Consider Carry Look-Ahead or Carry-Select Implementations to Improve Performance Carry Chains Longer Than 32 LEs Still Provide Performance and Utilization, but they degrade the Ease-Of-Fit Further Reading Quartus Online Help: Search for “Carry”

Carry Chain Construction
Function’s Carry Chain Can Begin in Any LE of a LAB Carry Chain Counter Starting at LE1 could be Faster, because Register feedback multiplexer is available on LE1 of each LAB Runs Downward through LEs of a LAB At End of LAB, Continues to Top of Second-Next LAB in Same Row Stops at ESB Stops at End of Row ... ESB ESB ...

Cascade Chain LAB-wide Synchronous Load LAB-wide Synchronous Clear Packing Register Select To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect Carry-In Cascade-In data1 Look-Up Table (LUT) Carry Chain Synchronous Load & Clear Logic PRN CLRN Cascade Chain data2 D Q data3 data4 ENA Asynchronous Clear/Preset/ Load Logic labclr1 labclr2 Chip-Wide Reset Clock & Clock Enable Select To FastTrack Interconnect, MegaLAB Interconnect, or Local Interconnect labclk1 labclk2 labclkena1 labclkena2 Carry-Out Cascade-Out

Cascade Chain Cascades LUT Outputs, Implementing High-Performance, Wide Fan-in Functions LE LUT in[3..0] LE2 LUT in[7..4] LEn LUT Result of Inputs in[0] to 4[n-1] in[4n (n-1)]

Without Cascade Chains: 3 LEs Using Cascade Chains: 2 LEs
Cascade Chain Example Without Cascade Chains: 3 LEs LE LUT in[2..0] in[5..3] in[7..6] result in0 in2 in1 in3 in4 in5 in6 in7 result 8-Input AND Gate Using Cascade Chains: 2 LEs LE in[3..0] LUT LE2 in[7..4] LUT result

Cascade Chain Construction
Starts in First LE (LE1) of Every LAB Function’s Cascade Chain Can Begin in Any LE of a LAB Runs Downward through LEs of a LAB At End of LAB, Continues to Top of Second-Next LAB in Same Row Stops at ESB Stops at End of Row ESB ESB ...

Cascade Chain Cascade Chains Can Improve Density, Performance
LEs Locked Together, Challenging Fitting of Logic Recommendations No More than 20% of APEX 20K Device Should Use Cascade Chains In General, Maximum Length Should Be 2 Carry Chains for Performance Cascade Chains Longer than 2 Carry Chains May Still Provide Utilization Advantages Further Reading Quartus Online Help: Search on “Cascade” * CJ: change 2 to 3

Architecture Features
User-Controlled Architectural Features Affects Performance & Utilization Carry Chain Arithmetic Functions Cascade Chain Wide Fan-in Functions These Features Are Controlled Using: Logic Options

APEX 20K I/O Element

APEX 20K IOE vs. APEX 20KE IOE Open-drain Operation
Faster Clock-to-Output for Open-drain Signals Programmable Delays APEX 20K - 2 modes (OFF and ON) APEX 20KE - 4 modes (OFF and 3 levels of delay) Column IOE Interconnect APEX 20K - IOE signals route to column interconnect APEX 20KE - IOE signals route to column and FastRow interconnect

Supported I/O Standards
 Note : Only the larger APEX devices will support LVDS. EP20K100E, EP20K160E, and EP20K200E will not support LVDS.

APEX 20K PLL Features Altera’s Next-Generation PLL
ClockLock™ Synchronization Circuitry ClockBoost™ Multiplication Circuitry (1X, 2X & 4X) Can Use Any Combination of Two ClockBoost Outputs Simultaneously Extended Frequency Range Can Use PLL Output to Clock Negative Edge Triggered Flip-Flops

ClockLock/ClockBoost ClockLock/ClockBoost
Simultaneous ClockLock/ClockBoost Circuitry Any Two Combinations of 1x, 2x, or 4x Possible PLL gclk1 ClockLock/ClockBoost clk1 Either Signal Can Drive Any LE, IOE, or ESB ClockLock/ClockBoost clk0 gclk0 When Any Combination of Two ClockBoost Outputs Are Used Simultaneously, Cannot Use GCLK0 Pin

APEX 20KE PLL Features Multiple PLLs Advanced ClockBoost Circuitry
2 or 4 Depending on Device Size Advanced ClockBoost Circuitry Supports m/(n*k) Multiplication m = , n =1 - 16, k = T1/E1 Conversion ( MHz <-> MHz) ClockShift Circuitry +- 2ns (0.5 ns precision) Delay Adjustment 90/180/270 Degrees Shifting Drive PLL Output Off-Chip with or w/o Feedback

Debugging Design Problems
Traditional board debugging techniques Probing nodes with a logic probe Capturing logic states or event activity With logic integration into a single chip it is very difficult to debug design problems Can’t get at internal nodes Difficult to probe BGA pins in the middle of the package Route buried signals to a pin Must change the design files & hierarchy to add the pin Changing the design could impact timing May also require the user to add the pins to the hierarchy symbols of the design. This can be cumbersome for more than two level or bringing out many pins

SignalTap Embedded Logic Analyzer
SignalTap is a synchronous Logic Analyzer (State Analyzer) that can capture the logic state of any hard node or pin in an APEX 20K device using a synchronous global clock

SignalTap gives the designer the ability to look at any node in their design while the circuit is running No modification to the design files is required Drag and drop nodes from the Node Finder Window Can monitor multiple nodes and record them in a Quartus waveform file for viewing

APEX 20K Device MasterBlaster Communications Cable

Summary Introduction to Altera & Altera Devices
Introduction to the Quartus development system Quartus design environment Quartus design methodology Design Entry Workgroup computing: Revision Control software Setting up the Project Compilation Introduction to APEX 20K and APEX 20KE Architectural features Carry Chain and Cascade Chain Review and Support

Altera Technical Support
Reference Quartus On-Line Help Consult Altera Applications (Factory Applications Engineers) Hotline: (800) 800-EPLD (6:00 a.m. - 6:00 p.m. PST) Field Applications Engineers: Contact Your Local Altera Sales Office Receive Literature by Mail: (888) 3-ALTERA FTP: ftp.altera.com World-Wide Web: Use Atlas (Altera Technical Support) Solutions to Search for Answers to Technical Problems View Design Examples View Customer Training Class Schedule & Register for a Class

Appendices

Appendices Section 1: More detail information on other EDA tools
Section 2: Quartus Scripting

Mentor Graphics: Leonardo Spectrum
Required Version: See Quartus Readme file File Format: Use EDIF file format Quartus Online Help: Using Other EDA Tools Using Leonardo & Quartus Setting Up the Quartus/Exemplar Logic Working Environment Quartus/Exemplar Leonardo Spectrum Software Requirements

Synopsys Design Compiler
Required Version: See Quartus Readme file File Format: Use EDIF file format Quartus Online Help: Using Other EDA Tools Using Design Compiler and FPGA Compiler & Quartus Quartus/Synopsys Software Requirements Setting Up Design Compiler & FPGA Compiler Configuration Files (setting up the .synopsys_dc.setup) Setting Up the DesignWare Interface (additional setup .synopsys_dc.setup) Quartus/Synopsys Interface File Organization (information on where files are located. Location of a sample .synopsys_dc.setup file)

Synopsys Design Compiler: libraries
Important Libraries apex20k-3.db (technology library) altera.sdb (symbol library) apex20k-3.sldb (link library, synthetic_library) DW_APEX20K-3 (DesignWare library)

Synopsys FPGA Express Required Version: File Format:
See Quartus Readme file File Format: Use EDIF file format, LMF, Tcl Quartus Online Help: Using Other EDA Tools Using FPGA Express & Quartus Quartus/Synopsys Software Requirements Note: No setup file to update (.synopsys_dc.setup file does not exist.) FPGA Express is a window-based software

Synplicity Required Version: File Format:
See Quartus Readme file File Format: Use Verilog file format Quartus Online Help: Using Other EDA Tools Using Synplicity & Quartus Quartus/Synplicity Software Requirements

Cadence Verilog-XL Required Version: File Format:
See Quartus Readme file File Format: Use Verilog file format Quartus Online Help: Using Other EDA Tools Using Verilog-XL & Quartus Setting Up the Quartus/Cadence Verilog-XL Working Environment Quartus/Cadence Verilog-XL Software Requirements

Model Technology ModelSim
Required Version: See Quartus Readme file File Format: Use Verilog or VHDL file format Quartus Online Help: Using Other EDA Tools Using ModelSim & Quartus Setting Up the Quartus/ModelSim Working Environment Using ModelSim & Quartus Software ModelSim Software Requirements

Synopsys Prime Time Required Version: File Format: Quartus Online Help
See Quartus Readme file File Format: Use Verilog file format Quartus Online Help

Synopsys MOTIVE Required Version: File Format:
See Quartus Readme file File Format: Use Verilog file format Quartus Online Help: Using Other EDA Tools Using MOTIVE & Quartus Setting Up the Quartus/MOTIVE Working Environment Performing Timing Verification of Verilog Output Files (.vo) with MOTIVE Software Quartus/Synopsys MOTIVE Software Requirements

Synopsys VSS Required Version: File Format:
See Quartus Readme file File Format: Use VHDL file format Quartus Online Help: Using Other EDA Tools Using Design Compiler and FPGA Compiler & Quartus Setting Up VSS Configuration Files Performing a Pre-Routing or Functional Simulation with VSS Software Altera Simulation Libraries

Quartus Scripting

Outline Scripting Overview Tcl/Tk Appendix

What is scripting? Used for “gluing” applications
Used for automating routine tasks Quartus supports Tcl scripting Scripting languages have very flexible data structures. For example, you can assign a variable a string value, then use this same variable as an integer. This flexibility allows scripting languages the ability to integrate different data structures of different applications. A script could take information from one application, modify its data structure and send it to another application rather easily. This integration is becoming more and more important, and scripting languages are gaining in popularity. Scripting can also be used for combining and automating routine tasks. For example, if you always want to compile and simulate a design, you could create a script which would do both of these things with a single statement. You can customize these scripts for whatever you are doing.

Running a Script in Quartus
Run Script Command Tools -> Run Script Console Window Command Line Arguments You can run a Tcl command or script three different ways in Quartus. You can use the Command Console, the Run Script option, or Command Line arguments.

Tcl/TK Console Console can be invoked using
View-> Auxiliary Windows-> Tcl/TK Console Pressing the button Messages will appear in the Message Window under the System tab You can use the Tcl/TK Console from Quartus to launch scripts and also to interactively run Tcl commands.

Command Line Mode Used for running Quartus in the batch mode
Quartus command usage : d:> \quartus\bin\quartus_cmd.exe - f <File Name> Insert Tcl script in <File Name> Quartus is invoked from the DOS Prompt or the UNIX shell quartus_cmd.exe is the command to run Quartus from the command prompt. Using quartus.exe will bring up the GUI You can run Tcl/TK scripts without ever launching the Quartus GUI. These scripts can set up projects, launch compilations, etc.

More Info : Command Line
quartus_cmd <project name> -c <csf> Compiles project with the specified Compiler Settings File (.csf) quartus_cmd <project name> -s <ssf> Simulates project with the specified Simulator Settings File (.ssf) quartus_cmd -h Displays the help information for the Command Line Currently, you must run the Command Line from the project directory. For example: D:\testing > d:\quartus\bin\quartus_cmd reg -c reg will allow you to run from any directory. For example : D:\Quartus\bin > quartus_cmd d:\testing\reg -c d:\testing\reg Currently, Quartus will not recognize the directory path to the project.

More Info : Command Line
Messages are written to DOS Window D:\testing > d:\Quartus\bin\quartus_cmd reg.quartus -c quartus.csf Info: Quartus Version A 2.4 6/21/1999 processing started at 06/23/99 09:09:33 Info: d:\testing\reg.bdf defines 1 design units and 1 entities. Info: Entity 1: reg Info: d:\testing\duplicate.bdf defines 1 design units and 1 entities. Info: Entity 1: duplicate Info: Logic Synthesizer created 4 element(s)... Info: 2 input pins Info: 1 output pins Info: 1 LCells Info: reg is automatically assigned to EP20K100TC144-1 Info: Fitting attempt 1 started at Wed Jun :09:52 Warning: Timing characteristics of device EP20K100TC144-1 are preliminary Warning: Design has registers and/or memories but no clock assignments. Quartus will try to automatically detect your clock pins and/or memory enable pins Info: Node |clk is assumed to be a clock. Info: No valid register-to-register paths exist for clock |clk Info: reg: Full compilation was successful. 0 errors, 2 warnings. Completed...

Quartus API Application Programming Interface (API) Functions
Pre-Defined Interface Functions The API allows for the following types of Tcl commands to interface with Quartus : Project control functions Project Compiler Simulator Device database functions Get device and timing information Source code control functions Interface with Revision Control software

Tcl/Tk Basics Tcl = Tool Command Language
Tk is an extension of Tcl, used for GUIs Works on PCs and Workstations Interpreted Programming Language Quartus uses Tcl/Tk version 8.0.3, supplied by Scriptics Quartus contains a Tcl text editor with syntax coloring Created by John Ousterhout in the late ‘80s. Tcl scripts are “interpreted” rather than compiled. This means that when you execute a Tcl script, it immediately starts executing, rather than check for syntax, etc. This speeds up development time, but could make it more difficult when debugging. Tcl Scripts are portable, meaning you can use the same Tcl script for a workstation and a PC.

Sets variable “var” equal to 3
Tcl Syntax Tcl is Case Sensitive Basic Syntax command arg1 arg2 arg3 … Example : set var 3 Command Substitution puts “The variable value is [expr $var + $var]” Writes “The variable value is 6” to the Message Window Variable Substitution puts “The variable value is $var” Writes “The variable value is 3” to the Message Window Sets variable “var” equal to 3 Name preceded by “$” is replaced with value of name Command within “ [ ] ” is replaced with results of command

Controlling Projects with Tcl
Tcl Project Commands can : Create a Project Open a Project Close a Project Check if a Project exists Make Project Assignments Get Project Assignments Tcl Project commands begin with the command “project” A listing of Tcl Project commands is found in the on-line help

Making Project Assignments with Tcl
Node or Entity Assignment project add_assignment [entity] “” “” [node/entity name] [assignment type] [value] Example : project add_assignment chiptrip “” “” |chiptrip|clock GLOBAL_SIGNAL ON Clique Assignment project add_assignment [entity] [clique name] “” [instance name] MEMBER OF [clique name] Example project add_assignment chiptrip clique1 “” auto_max|my_register MEMBER_OF clique1

Controlling the Compiler with Tcl
Tcl can access the Quartus compiler Tcl compiler commands can : Start compilation Stop compilation Make compiler assignments Get compiler assignments Tcl Compiler commands begin with the command “cmp” A listing of Tcl Compiler commands is found in the on-line help

Making Compiler Assignments with Tcl
Assign a device cmp add_assignment [chip name] "" "" DEVICE [device] Example : cmp add_assignment chiptrip "" "" DEVICE EP20K400BC652-3 Assign a pin cmp add_assignment [chip name] "" [pin] LOCATION [device] cmp add_assignment chiptrip “” |clock LOCATION pin_U2

Controlling the Simulator Via Tcl
The Quartus simulator supports Tcl testbenches Tcl Simulation commands can : Force and release values Stop, Start, Pause simulation Get debug info about the simulation Read and write data from memory Tcl Simulation commands begin with the command “sim” A listing of Tcl Simulation commands is found in the on-line help

Example Tcl Simulation Testbench
project open chiptrip project set_active_sim chiptrip sim initialize while { [sim is_initialized] } { after 10; # sleep FlushEventQueue # flush messages } sim testbench_mode true sim print info “Simulation is initialized” sim force_value {dir\[0\]} 0 # dir[0]=0 sim force_value {dir\[1\]} 1 # dir[1]=1 sim force_value clock 0 # clock = 0 sim run 10ns # simulate for 10ns sim force_value clock 1 # clock = 1 sim get_value at_altera # get output value sim run end Quartus does not create a graphical waveform of a Tcl Testbench “get_value” writes text output to Tcl console output can also be piped to an output file using : puts $outputFile [sim get_value at_altera] node/pin name Time dir[0] dir[1] clock at_altera X Example Output File created by User

Extending Quartus Tcl Commands
Create procedures and libraries to customize and extend capabilities >> source <your lib>.tcl >> example in1 in2 <your lib>.tcl proc example { input1 input2 } { … }

Tcl Procedure for Base Clock Assignments
# # # Description: Add a base or absolute clock # add_base_clock [Clock Name] [Fmax] [Include Pin Delays in Calculation] [Duty Cycle] proc add_base_clock {name fmax do_system duty} { if {$name != ""} { project add_assignment "" $name "" "" BASE_CLOCK $name } if {$do_system != ""} { project add_assignment "" $name "" "" DO_SYSTEM_FMAX $do_system if {$fmax != ""} { project add_assignment "" $name "" "" REQUIRED_FMAX $fmax if {$duty != ""} { project add_assignment "" $name "" "" REQUIRED_DUTY_CYCLE $duty This information gets written into Project Settings File (.psf)

Using Tcl Base Clock Procedure
Source <base_clock lib>.tcl add_base_clock mybase_clk 50MHz OFF 50 Assignment gets stored in Project Settings File (.psf) CLOCK(mybase_clk) { BASED_ON_CLOCK_SETTINGS = mybase_clk; INCLUDE_PIN_DELAYS_IN_CALCULATIONS = OFF; FMAX_REQUIREMENT = 50MHz; DUTY_CYCLE = 50; } This information gets written into Project Settings File (.psf)

Tcl Procedure for Relative Clock Assignments
# # # Description: Add a project relative clock # add_relative_clock [Clk Name] [Based on Clk] [* Base By] [/ Base By] [Base Offset] [Invert Base] proc add_relative_clock {name base multiply divide offset invert} { if {$name != ""} { project add_assignment "" $name "" "" BASE_CLOCK $base } if {$multiply != ""} { project add_assignment "" $name "" "" MULTIPLY_BASE_CLOCK_BY $multiply if {$divide != ""} { project add_assignment "" $name "" "" DIVIDE_BASE_CLOCK_BY $divide if {$offset != ""} { project add_assignment "" $name "" "" OFFSET_FROM_BASE_CLOCK $offset if {$invert != ""} { project add_assignment "" $name "" "" INVERT_BASE_CLOCK $invert

Using Tcl Relative Clock Procedure
Source <add_relative_clock lib>.tcl add_relative_clock new_clk_name mybase_clk off Assignment gets stored in Project Settings File (.psf) CLOCK(new_clk) { BASED_ON_CLOCK_SETTINGS = mybase_clk; MULTIPLY_BASE_CLOCK_PERIOD_BY = 2; DIVIDE_BASE_CLOCK_PERIOD_BY = 1; OFFSET_FROM_BASE_CLOCK = 0; }

For More Tcl Info Quartus on-line help http://www.scriptics.com
"Practical Programming in Tcl and Tk," Brent Welch. Prentice Hall, nd Ed. "Effective Tcl/Tk Programming," Mark Harrison and Michael McLennan, Addison-Wesley, 1997. "Tcl and the Tk Toolkit," John Ousterhout, Addison- Wesley, 1994.

Appendix: Tcl Project API

Appendix: Tcl Compiler API

Appendix: Tcl Simulator API

Introduction to Quartus and the APEX 20K Device Family

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