1. Overview Parallel Processing Pipelining
Characteristics of Multiprocessors
Interconnection Structures
Inter processor Arbitration
Inter processor Communication and Synchronization

2. Inter Processor Arbitration
Bus : facilitate the transfer of instruction between component
- bus used by CPU to connect processor register to ALU
1) Memory Bus ) I/O Bus
System Bus –
- A Backplane level bus
- Printed Circuit Board
- Connects CPU, IOP, and Memory
- Each of CPU, IOP, and Memory board can be
plugged into a slot in the backplane(system bus)
- Bus signals are grouped into 3 groups
Data, Address, and Control(plus power)
- Only one of CPU, IOP, and Memory can be
granted to use the bus at a time
- Arbitration mechanism is needed to handle
multiple requests
A bus that connects major component in a multiprocessor system , such
As CPUs, IOPs, and memory
e.g. IEEE standard 796 Multibus
- 86 lines
Data: (multiple of 8)
Address: 24
Control: 26
Power:

3. Synchronous and Asynchronous Data Transfer
Synchronous Bus
Each data item is transferred over a time slice known to both source and destination unit
- Common clock source
- Or separate clock and synchronization signal
is transmitted periodically to synchronize
the clocks in the system
Asynchronous Bus
Each data item is transferred by Handshake mechanism
- Unit that transmits the data transmits a control
signal that indicates the presence of data
- Unit that receiving the data responds with
another control signal to acknowledge the
receipt of the data
Strobe pulse - supplied by one of the units to indicate to the other unit when the data transfer has to occur

4. Inter Processor Static Arbitration
Serial Arbitration Procedure
Parallel Arbitration Procedure
Bus
arbiter 1 PI PO
arbiter 2
arbiter 3
arbiter 4
Highest
priority 1
Bus busy line
To next
arbiter
Ack
Req
4 x 2
Priority encoder
2 x 4
Decoder

5. InterProcessor Dynamic Arbitration
Priorities of the units can be dynamically changeable while the system is in operation
Time Slice
Fixed length time slice is given sequentially to each processor, round-robin fashion
Polling
Unit address polling - Bus controller advances the address to identify the requesting unit
LRU : highest priority to device that has not used bus for longest interval
FIFO : Requests are served in the order received.
Rotating Daisy Chain : PO of the last device connected to PI of first device
Conventional Daisy Chain - Highest priority to the nearest unit
to the bus controller
Rotating Daisy Chain - Highest priority to the unit that is
nearest to the unit that has most
recently accessed the bus(it
becomes the bus controller)

6. Interprocessor Communication
Shared Memory
Communication Area
Receiver(s)
Mark
Sending
Processor
Receiving .
Message
Instruction
Interrupt

7. In addition to shared memory , a multiprocessor system may have other
shared resources. For example : Magnetic disk
To prevent conflicting use of shared resources by several processor there
must be a provision for assigning resources to processors.
This task is given to OS
Three organizations that have been used to design OS for multiprocessor
(1) Master Slave Mode
(2) Separate Operating System
(3) Distributed Operating System

8. Inter Processor Synchronization
Communication of control information between processors
- To enforce the correct sequence of processes
- To ensure mutually exclusive access to shared writable data
Hardware Implementation
Mutual Exclusion with a Semaphore
Mutual Exclusion
- One processor to exclude or lock out access to shared resource by
other processors when it is in a Critical Section
- Necessary to protect data from being changed simultaneously by
two or more processors
- guarantees orderly access to shared memory and other shared
resources
- Critical Section is a program sequence that, once begun, must
complete execution before another processor accesses the same
shared resource

9. Inter Processor Synchronization
Semaphore
- A binary variable
1 : A processor is executing a critical section, that not
available to other processors
0 : Available to any requesting processor
- Software controlled Flag that is stored in memory that all
processors can be access
- Processor use shared segment when semaphore=0, they set it 1
when they are executing and clear it to 0 when finished.
A semaphore can be initialized with test and set instruction along with
hardware lock mechanism
TSL SEM
R  M [SEM] // Test Semaphore
M[SEM]  // Set Semaphore

10. The End