1. TODAY’S OUTLINE Testbench Circuit Verilog Operators
Concatenation operator
Logical operators
Bitwise operators
Conditional operators
Shift operators
Equality operators
Reduction operators
Arithmetic operators

2. Testbench
A testbench is an environment which surrounds a DUT (Design Under Test) and forces stimulus into the DUT while monitoring the output ports of the DUT
In other words, a testbench is an environment to verify the functionality of a design

3. Cont..
input
DUT
output
Testbench

4. How does waveform looks like?
Example
Testbench
module ANDgate_tb ();
reg A, B;
wire Y;
integer i;
initial
begin
for (i=0; i<4; i=i+1)
{A, B} = i;
#10;
end
ANDgate ANDgate_inst (A, B, Y);
endmodule
How does waveform looks like?
DUT
module ANDgate (A, B, Y);
input A, B;
output Y;
reg Y;
(A or B)
begin
Y = A & B;
end
endmodule

5. TODAY’S OUTLINE Testbench Circuit Verilog Operators
Concatenation operator
Logical operators
Bitwise operators
Conditional operators
Shift operators
Equality operators
Reduction operators
Arithmetic operators

6. Concatenation Operator
Single bits of signal can be combined to form a bus or multi-bits signal
The concatenation operator is identified by the symbol “{” and “}”
Example:
module ………;
input [1:0] A, B, C;
assign output = {A, B, C};
endmodule

7. Logical Operators
Logical operators return a single bit result. It is either “1” (true) or “0” (false).
Operation
Symbol
and
&& or ||
not !

8. Example Sketch the output waveform.. module test1 (A, B, C, D, Y);
input A, B, C;
input [2:0] D;
output [2:0] Y;
reg Y;
assign Y = D || {A, B, C};
endmodule
Sketch the output waveform..

9. Bitwise Operators
Bitwise operators operate on buses and return the result in bus form
Operation
Symbol
and
& or |
not ~
xor ^

10. Try to avoid using logical operator
Example
module test1 (A, B, C, D, Y);
input A, B, C;
input [2:0] D;
output [2:0] Y;
reg Y;
assign Y = D | {A, B, C};
endmodule
Try to avoid using logical operator
Sketch the output waveform..

11. Conditional Operators
Conditional operators are widely used for conditional checking
Commonly used to model combinational logic
Consist of 3 operands: input, select/control and output

12. Example module ……; assign Y = control ? inputA : inputB; endmodule
Conditional operators can be use to represent multiplexer

13. Shift Operators Two types of shift operator
Shift left for shifting left
Shift right for shifting right
Shift right is identified by symbol “>>”
Shift left identified by symbol “<<”

14. Example module ……; assign Y = inputA << 1; endmodule module ……;

15. Equality Operators Two types of equality operator: Logical equal
- identified by symbol “==” for equal and “!=” for not equal
- results returned are either “0” (false), “1” (true) or “X” (unknown)

16. Cont…
Case equal
- identified by symbol “===” for equal and “!==” for not equal
- always produces results that are “1” (true) or “0” (false)
- can identify values of “X” and “Z”

17. Example module ……; if (inputA == 1’b1) outputA = 1; else outputA = 0;
if (inputA != inputB)
outputA = 0;
else outputA = 1;
endmodule

18. Reduction Operators
Reduction operators are functionally the same as logical operators, except that it operates on itself
6 types of reduction operators:

19. Cont..
Operation
Symbol
and
& or |
xor ^
nand
~&
nor ~|
xnor ~^

20. Example module …….; assign outputA = &inputA;
endmodule

21. Arithmetic Operators 4 types of arithmetic operators: Operation Symbol
addition +
subtraction -
multiplication *
division /

22. Assignments
Write a Verilog code with a module named ‘exercise1’ and the interface signals shown:
- function of outputA is logical NOT of inputA
- function of outputB is logical OR of inputC or inputA
- function of outputC is logical AND of inputC and inputA
- function of outputD is logical AND of inputD and concatenation of inputA, inputB and inputC

23. Cont..
Create a testbench for the design exercise1 and sketch the waveform based on the stimulus written.
Noted, outputD and inputD is 3-bit. InputA, inputB and inputC are 1-bit.

24. Cont..
Write a Verilog code with a module named ‘exercise2’ and the interface signals shown:
- function of outputA is bitwise NOT of inputA
- function of outputB is bitwise OR of inputC or inputA
- function of outputC is bitwise AND of inputC and inputA
- function of outputD is bitwise AND of inputD and concatenation of inputA, inputB and inputC

25. Cont..
Create a testbench for the design exercise2 and sketch the waveform based on the stimulus written.
Noted, outputD and inputD is 3-bit. InputA, inputB and inputC are 1-bit.

26. Cont..
3. Write a Verilog code using conditional operators with a module named “exercise3” based on schematic below.
inputA 1
outputY
inputB 1
inputC
Sel[1:0]

27. Cont..
Create a testbench for the design exercise3 and sketch the waveform based on the stimulus written.

28. Cont..
4. Write a Verilog code with a module named ‘exercise4’ for the arithmetic operation below:
- function of outputW is arithmetic operation of inputA add inputB
- function of outputX is arithmetic operation of inputA substract inputB
- function of outputY is arithmetic operation of inputA multiply inputB
- function of outputZ is arithmetic operation of inputA divide inputB

29. Cont..
Create a testbench for the design exercise4 and sketch the waveform based on the stimulus written.
Noted, all inputs and outputs are 4-bit.

30. Lab 1 (Introduction to ModelSim)
will start on next week.. Be prepared..
That’s all for today.
See u on Tuesday (25 July 2006), 8.30am..