1. High-Speed/Low Power At Architectural Level
The Circuit Under Study
Behavioral Simulations to Verify Functionality
Speed & Area & Power Results, Through Synthesis with 1.6V Default in CMOSP18 Cell Library
Xiao Xing

2. The Circuit Under Study

3. Behavior Simulations (Combinational)

4. Behavior Simulation (2-Stage Pipeline)

5. Behavior Simulation (4-Stages Pipeline)

6. Behavior Simulation (8-Stages Pipeline)

7. Behavior Simulation ( 2 Combinational Multipliers In Parallel)

8. Behavior Simulation (2 2-Stage Pipelines In Parallel

9. Version of Array Multiplier
Purely-Combinational
2 Pipe-Lines
4 Pipe-Lines
8 Pipe-Lines
2 Combos In Parallel
2 2-Stage Pipelines In Parallel
Area
Combinational
Sequential
Total Cell Area
Frequency/Throughput
1 / ns = 66 MHz
1/8ns = 125 Hz
1/4ns = 250 MHz
1/3ns = 333 MHz
1/15ns = 66 MHz
1/9ns = 111 MHz
Power
Cell Internal Power
3.9025mW (43%)
1.088 mW mW mW
uW (60%)
2.188 mW (73%)
Net Switching Power
mW (57%)
uW (26%)
uW (20%)
uW (12%)
uW (40%)
uW (27%)
Total Dynamic Power
mW (100%)
mW (100%)
mW (100%)
mW (100%)
mW (100%)
mW (100%)
Cell Leakage Power nW nW nW nW nW
1.1654uW

10. Comparison of Total Cell Area

11. Comparison of Frequency/Through-Put

12. Comparison of Power

13. Summary
8-Stage Pipeline is the most Area, Power Consuming, but also the Fastest of all Array Multipliers Implemented
While 8-Stages is twice of 4-stages in terms of area and Power, its only about 1.3 Times Better in Speed (Diminishing Return), confirming the prediction that one can NOT Gain Infinitely Speed, in Simply Increasing the number of Pipeline Stages
With Parallelism, one Should Gain consistent Twice the Speed, at Twice the Area and Power Consumed; But Clock/Data Skew becomes a problem with Larger Parallelism, even if Power And Area is of no Issue
2 2-Stage Parallel Array Multiplier, is the 2nd Fastest, Most Power/Area Consuming; 4-Stage Pipeline come close to it in every department

14. Possible Enhancements
Gate-Level Net List Simulation to Verify, real life Functionalities and Performances
Correct the Synthesis Result for the Purely Combinational Array Multiplier
Performance and cost of 4 and 8 Pipelines In Parallel

15. References
[1] Jia Di, J. S. Yuan and R. DeMara, Improving Power-awareness of Pipelined Array Multipliers using 2-Dimensional Pipeline Gating and its Application on FIR Design, Integration, the VLSI Journal, Vol. 38,No. 3, February 2005
[2] Jan, M Raebey, Digital Integrated Circuits, 2nd Edition, Prentice Hall,2003
[3] John R, Calvert, Design of a Synchronous Pipelined Multiplier and Analysis of Clock Skew in High-Speed Digital Systems, NAVAL POSTGRADUATE SCHOOL MONTEREY CA , Dec 2000
[4] Daniel J. Sorin, Pipelining and Advanced Topics, Jan 2005