1. TIMING DIAGRAM OF 8085

2. INSTRUCTION CYCLE
The time required to execute an instruction is called instruction cycle.

3. MACHINE CYCLE
The time required to access the memory or input/output devices is called machine cycle.

4. T-STATE
The machine cycle and instruction cycle takes multiple clock periods.
A portion of an operation carried out in one system clock period is called as T-state.

5. MACHINE CYCLES OF 8085
The 8085 microprocessor has 5 basic machine cycles.
They are
Opcode fetch cycle (4T/6T)
Memory read cycle (3 T)
Memory write cycle (3 T)
I/O read cycle (3 T)
I/O write cycle (3 T)

6. MACHINE CYCLES OF 8085
The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states.
One T-state is equal to the time period of the internal clock signal of the processor.
The T-state starts at the falling edge of a clock.

7. TIMING DIAGRAM Timing Diagram is a graphical representation.
It represents the execution time taken by each instruction in a graphical format.
The execution time is represented in
T-states.

8. Timing Diagram
Representation of Various Control signals generated during
Execution of an Instruction.
Following Buses and Control
Timing Diagram:
•Higher Order Address Bus.
Signals
must be
shown in a
•Lower Address/Data
•ALE
•RD
•WR
•IO/M
bus

9. CONTROL SIGNALS

10. OPCODE FETCH MACHINE CYCLE OF 8085

11. OPCODE FETCH MACHINE CYCLE OF 8085
Each instruction of the processor has one byte opcode.
The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch the opcode from memory.
Hence, every instruction starts with opcode fetch machine cycle.
The time taken by the processor to execute the opcode fetch cycle is 4T.
In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.

12. MEMORY READ MACHINE CYCLE OF 8085

13. MEMORY READ MACHINE CYCLE OF 8085
The memory read machine cycle is executed by the processor to read a data byte from memory.
The processor takes 3T states to execute this cycle
The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle.

14. MEMORY WRITE MACHINE CYCLE OF 8085

15. MEMORY WRITE MACHINE CYCLE OF 8085
The memory write machine cycle is executed by the processor to write a data byte in a memory location.
The processor takes, 3T states to execute this machine cycle

16. Timing Diagram Instruction: A000h MOV A,B Corresponding Coding: A000h
T T T T4
A15- A8 (H
00h
ALE
A0h
bus)
MOV A,B
A15- A8 (Higher Order Address
Corresponding Coding:
78h
A000h 78 I RD
OFC WR
O/M
Memory I
8085
Op-code fetch Cycle

17. Timing Diagram Instruction: A000h MVI A,45h Corresponding Coding:

18. Timing Diagram Instruction: A000h MVI A,45h Corresponding Coding:
OFC
A000h
A001h 3E 45
MEMR
Memory
8085

19. Timing Diagram Instruction: A000h MVI A,45h Corresponding Coding:
ALE T1 T5
01h T6
A0h T7 T2 T4
bus)
A0h T3 0h
er address
Lower ord
A15- A8 (Higher Order Address
00h
3Eh
45h
DA7-DA0 (
er address/data Bus)
Instruction:
A000h
MVI A,45h
Corresponding Coding: I RD
A000h
A001h 3E 45 WR
O/M I
Op-Code Fetch Cycle
Memory Read Cycle

20. Timing Diagram Instruction: A000h LXI A,FO45h Corresponding Coding:21 45 F0

21. Corresponding Coding:
Timing
Diagram
Instruction:
A000h
LXI A,FO45h
Corresponding Coding:
OFC
A000h
A001h
A002h 21 45 F0
MEMR
MEMR
Memory
8085

22. Memory Read Cycle Memory Read Cycle Op-Code Fetch Cycle A15- A8 (H ALE
Timing Diagram
Op-Code Fetch Cycle
Memory Read Cycle
Memory Read Cycle T1 T2 T3 T4 T5 T6 T7 T8 T9
T10
A15- A8 (H
00h
DA7-DA0 (
ALE A
Lower ord
er address
bus)
01h
A0h
02h
A0h F
A0h
A15- A8 (Higher Order Address
21h
45h
F0h
DA7-DA0 (
er address/data Bus) I RD
O/M WR

23. Timing Diagram Instruction: A000h MOV A,M Corresponding Coding: A000h

24. Timing Diagram Instruction: A000h MOV A,M Corresponding Coding: A000h
OFC
Corresponding Coding:
MEMR
A000h 7E
Memory
8085

25. Timing Diagram Instruction: A000h MOV A,M Corresponding Coding: A000h
A15- A8 (H
00h
DA7-DA0 (
ALE T2 7
Lower ord T3
er address T4
bus) T5 C
L Reg T6
Conte T7
A0h
Content Of Reg H
A15- A8 (Higher Order Address
7Eh
Content Of M
Instruction:
DA7-DA0 (
er address/data Bus)
A000h
MOV A,M
Corresponding Coding:
A000h 7E I RD WR
O/M I
Op-Code Fetch Cycle
Memory Read Cycle

26. Timing Diagram Instruction: A000h MOV M,A Corresponding Coding: A000h77

27. Timing Diagram Instruction: A000h MOV M,A Corresponding Coding: A000h
OFC
MOV M,A
Corresponding Coding:
MEMW
A000h 77
Memory
8085

28. Timing Diagram Instruction: A000h MOV M,A Corresponding Coding: A000h
A15- A8 (H
00h
DA7-DA0 (
ALE T2 A 7
Lower ord T3 0h
er address T4
bus) T5 C
L Reg T 6
Content T7
of Reg A A
Content Of Reg H
A15- A8 (Higher Order Address
7Eh
Instruction:
DA7-DA0 (
er address/data Bus)
A000h
MOV M,A
Corresponding Coding:
A000h 77 I RD WR
IO/M
Op-Code Fetch Cycle
Memory Write Cycle

29. I/O READ CYCLE OF 8085
The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral.
The processor takes 3T states to execute this machine cycle.
The IN instruction uses this machine cycle during the execution.

30. I/O READ CYCLE OF 8085

31. I/O WRITE CYCLE OF 8085
The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a peripheral, which is I/O, mapped in the system.
The processor takes, 3T states to execute this machine cycle.

32. I/O WRITE CYCLE OF 8085

33. EXAMPLE INSTRUCTION : MVI B, 43

34. EXAMPLE INSTRUCTION : STA 526A