1. Adapting the via last Design
Full 3D will require significant developments in active edge sensor processing and wafer bonding to clearly be affordable. It will be very difficult to achieve this by the 2014 TDR.
The track/tracklet concept does not depend the aggressive 3D technology – look at a more conservative alternative
Because the sensor pixel pitch is large, we can use via-last technology, which is much more conservative, to design a compact bump-bonded module. CERN has pioneered this with IPEDIA
Look at a variant of the CERN module to accommodate the long barrel
We will also explore using this module without major modifications
Design uses only coarse pitch bump bonding and wirebonding
Large pitch and diameter (60 micron) TSVs

2. Analog signals Top detector Amp/disc cluster and stub formation
Interposer
Long (1 cm) strips
Short (1.25 mm) strips
Top detector
Long (2.5 cm) strips
Short (1.25 mm) strips
Spacer
Readout Chip
TSV
Flex Jumper
Readout bus

3. Chip in the middle
Chip on the bottom
Chip on top

4. Chip on Top Edge Region
wirebond
Bump bonds
TSV
Readout Chip
Top Sensor
Flex Jumper
750m
Foam Spacer
Bottom Sensor
250m
wirebond

5. Carbon fiber support beam
module
RVC foam spacer
5 cm
5 cm
foam spacer
4 cm
4 cm
Carbon fiber support beam
foam spacer

7. Design features
D0 Layer 0
The readout chips are via-last – TSVs are drilled in wafers after CMOS fabrication
almost any CMOS process can be used.
Chips must be thicker – 250 microns vs about 20
Top to bottom connections by flex cable.
We have experience with these for D0
Long strip connections to ROIC by wirebond rather than bump
Readout bus connections by wirebond –bus sits on IC
Long strips longer – 2.5 vs 1 cm.
Spacers must be thermally conductive –RVC foam
Twice as many modules – we will need to stagger them in radius to minimize dead area
Smaller module means more GBTs/DC-DC converter or more complex interconnect
Analog cable
Flex foldover

8. CERN Discussions
Collaboration on pixel/strip readout chip We discussed the possibility of collaborating on the pixel readout chip. The major difference between the CERN and Fermilab designs is the use of an asychronous pipeline in the Fermilab design.There are certainly common features, including cluster finding and stub finding as well as event storage.  CERN also now has a 65nm front end design.  It would be beneficial in a number of ways if we could collaborate, perhaps on two variants, including common blocks for much of the design, but with a pipelined and clocked variant.  If it makes sense we might use the end-of-November pixel chip visit for more detailed discussions. We will also investigate a variant which includes the long strip amplifier/discriminator into the pixel chip.
Study of CERN modules in track/tracklet design We will examine possible arrangement of the CERN modules into a stack suitable for tracklet/track finding.  Duccio will provide drawings.
VIA last We will collaborate with CERN in exploring an alternate vendor for via-last technology. I have been in contact (and have a quote from) Allvia.   - CERN wafers I have asked Allvia what information is needed to quote on TSV fabrication on theexisting CERN wafers. Sandro has offered to provide two bumped and two nonbumped wafers.   - Module-specific We will also look at fabrication of dummy via-last wafers which can be used for testing prototype modules.

9. Status Discussion
Active edge testing Bump bonding of VICTR to Sensor (UCD) Bump bonding of full wafers to PCB interposer Active edge top wafer Mechanics and cooling Off-detector processing