1. SRAM Design for VFAT3/GdSP
CERN - Jérôme Masson
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

2. SRAM Design for VFAT3/GdSP - CERN
Outline
Objectives
Some results of the design of SRAM1
Future prospects
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

3. SRAM Design for VFAT3/GdSP - CERN
Objectives
Perform a new implementation of memory modules for VFAT3/GdSP development
Why?
IBM CMOS 130 nm Dual Port (= key point)
Bypass the issue
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

4. SRAM Design for VFAT3/GdSP - CERN
Idea: divide SRAM1 in several little modules of 128 x 64
OK but… need to control the modules
M_1
M_10
M_1
………
M_10
128
SRAM1
M_1
M_10
800
latency
read ptr
write ptr
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

5. SRAM1 & Decoder Module Module FIFO Module Mux Address Decoder Encoder
data IN 128 channels
Module
data OUT 128 7 7 7
address
address
address
Mux
read_address
Address
Decoder
read_address 11 7
write_address
write_address
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

6. Test bench of the Decoder
No encoding and decoding yet
Pseudo random number generator
Random
data 11
data_in
Counter
0  1279
read_address
read_address 7 11
write_address 7
Row of 10 modules +
10 mux
Address
Decoder
Under
Test
write_address
read_en 10 1
read_en 1
write_en 10
write_en
clk
mux_selection 10
resetb
stimulus
data_out
Control Logic
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

7. Results Current simulation : Results :
1 Decoder under test with 10 memory modules
Results :
Dual port OK (each cycle)
If stop writing during the process  no disturbance
If reset ON  start from the beginning (OK)
Once the 10 modules are filled in for the 1st time  back to the 1st module (OK)
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

8. Hamming data ENCODED Hamming encoders HE3 38 (38,32) data IN 32 HE2
152
128
HE1 (38,32)
HE0
(38,32)
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

9. Hamming data ENCODED with INTERLEAVED bits Hamming encoders HE3 38
(38,32) 38
data IN 32
HE2
(38,32)
Module
(SRAM1)
152
128
HE1 (38,32)
HE0
(38,32)
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

10. Future prospects Encoding and decoding blocks  simulation
When it looks good  control logic for REAL stimulus (or before ?)
And then…
FIFO design or synthesis/placing&routing of SRAM1 ?
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN

11. Thank you for paying attention
April 11, 2013
SRAM Design for VFAT3/GdSP - CERN