1. Digital Integrated Circuits A Design Perspective
EE141
Digital Integrated Circuits A Design Perspective
The Inverter

2. The CMOS Inverter: A First Glance
out C L DD
-Nucleus of ICs
-Analysis can be extended to study
Complex logic gates (NAND/NOR/XOR)
Cost (complexity and area)
Robustness (static/steady state behavior)
Performance (dynamic/transient response)
Energy efficiency (power/energy consumption)

3. CMOS Inverter N Well V DD PMOS 2l Contacts Out In Metal 1 Polysilicon
NMOS
GND

4. Two Inverters
Share power and ground
Abut cells
Connect in Metal

5. CMOS Inverter First-Order DC Analysis
VOL = 0
VOH = VDD
VM = f(Rn, Rp) V DD in =
out R n p
Low and High o/p levels equal
VDD and GND (High Noise Margin)
Ratioless (logic levels do not
depend on device sizes)
Vout is always connected to either
VDD or ground (Low o/p impedance)
therefore, Less sensitive to noise.
High i/p impedance (Fanout-large)
No static power dissipation

6. CMOS Inverter: Transient ResponseDD DD t
pHL
= f(R on .C L )
= 0.69 R C R
Charging p V
out V
out C
-For building fast
gates, keep either
CL small or decrease
the ON resistance
of FET
-RON is decreased by
Increasing W/L ratio
NOTE:RON is not fixed L C L R n
discharging V = V = V in in DD
(a) Low-to-high
(b) High-to-low

7. Voltage Transfer Characteristic

8. CMOS Inverter Load Characteristics

9. CMOS Inverter VTC
res: Resisitive/ON VM

10. Switching Threshold as a function of Transistor Ratio10 1
0.8
0.9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8 M V
(V) W p /W n
-VM is insensitive to small variations in W/L , ie., VTC remains unaffected
-Increasing W of PMOS or NMOS moves VM towards VDD or GND
VM=(rVDD)/(1+r)

11. (W/L)p= (W/L)n X (VDSATn K’n)/ (VDSATp K’p)
VM=(rVDD)/(1+r) considering VDD is very large
VM= VDD/2 when r =1
To move VM upwards, a larger value of r is required, which means making the
PMOS wider (stronger).
Strengthening the NMOS on the other hand, moves VM closer to GND
(W/L)p= (W/L)n X (VDSATn K’n)/ (VDSATp K’p)

12. Changing the inverter threshold can improve the circuit reliability

13. Determining VIH and VIL (Noise Margin)OH OL in
out M IL IH
A simplified approach

14. Inverter Gain CLM consider (1+λVout) Find dVout/dVin = g by ignoring
some second order terms
-high gain in transition
region (useful for amplifier
applications)
ID(VM) is current when Vin=VM
previous equation: equating saturation currents
of PMOS and NMOS and then differentiating to find
dVout/dVin = g ; put VM = Vin

15. #
an inverter in 0.25 um technology
PMOS to NMOS ratio of 3.4
NMOS transistor minimum size (Wn=0.375 um Ln=0.25 um) (59 uA)
VM=1.25 V
--Find gain g
-- Find Noise Margins
(* First find ID(Vin=VM); use k’n = 115 x , k’p = 30 x 10-6 ,VDSATn= 0.63 V,
VDSATp= 1.0 V, VTn=0.43 V, VTp=0.4 V, λn=0.06, λp= -0.1 ;
THEN find ‘g’ and then noise margins)
Simulate an inverter with same parameters and compare the calculated and
simulated results

16. Inverter Gain calculated values of:
VIL= 1.2 V, VIH = 1.3 V, NML=NMH = 1.2 V
Inverter Gain
simulated VTC and gain in 0.25 um process
The actual values of VIL= 1.03 V, VIH = 1.45 V, NML= 1.03 V, NMH = 1.05 V

17. #calculated values of:
VIL= 1.2 V, VIH = 1.3 V, NML=NMH = 1.2 V
#The actual values of VIL= 1.03 V, VIH = 1.45 V, NML= 1.03 V, NMH = 1.05 V
These values are lower than those predicted; for two reasons
1) Gain equation overestimates the gain. From gain plot, the maximum gain (at VM)
equals only 17. This reduced gain would yield values for VIL and VIH of 1.17 V
and 1.33 V. (operating conditions: velocity saturation ?)
2) The gain expression are useful as first order approximations only.

18. Supply Voltage (VDD) Scaling
*trend is to reduce device dimensions and supply voltage,
however, threshold voltage is kept constant
subthreshold operation
Low switching current/slow
Operation (watches)
-sensitive to noise (N don’t scale)
Gain=-1
Reducing VDD improves gain
Gain deteriorates at very low supply voltages

19. Why not opt for low voltage operation when the high gain
can be achieved at lower supply voltages ?

20. Why not opt for low voltage operation when the high gain
can be achieved at lower supply voltages ?
--delay ?
--sensitive dc characteristics ?
--noise sensitive ?
Supply must be at least a couple times φT =kT/q (=25 mV at room temperature), thermal noise becomes an issue in unreliable operation.
The only way to get CMOS inverters to operate below 100 mV is to reduce the ambient temperature, or in other words to cool the circuit.

21. Impact of Process Variations (Robustness)
0.5 1
1.5 2
2.5 V in
(V)
out
Good PMOS
Bad NMOS
Good NMOS
Bad PMOS
Nominal
The good device has smaller tox(-3nm), smaller L(-25nm), higher W(+30nm), smaller threshold
(-60mV)
*Operation of the gate is insensitive to process variations

22. Parasitics affecting delay

23. Parasitics affecting delay
M1 and M2 are either in cut-off or in the saturation mode (up to 50%
point) of the output transient.
gate-drain capacitors: Cgd12 = 2 CGD0W (with CGD0 the overlap capacitance per unit width as used in the SPICE model). [*Miller effect]
(non-linear)
A multiplication factor Keq is introduced to relate the linearized
capacitor to the value of the junction capacitance under zero-bias conditions.

24. [Dally 98]

25. Parasitics affecting delay

26. Problem…
Find Keq and Keqsw

28. Solution…

29. Solution…

30. Fan-out distance and number
Length, width,
Fan-out distance and number
*It assumes that all components of the gate capacitance are connected between Vout and GND (or VDD), and ignores the Miller effect on the gate-drain capacitances.
Second approximation is that the channel capacitance of the connecting gate is constant over the interval of interest.
[10% error]

32. 0.25 um CMOS technology. VDD = 2.5 V.
From the layout, derive the transistor sizes, diffusion areas, and perimeters.
As an example, we will derive the drain area and perimeter for the NMOS tran-
sistor. The drain area is formed by the metal-diffusion contact, which has an area of
and the rectangle between contact and gate, which has an area of
This results in a total area of AD=
The perimeter of the drain area is rather involved and consists of the following components (going counterclockwise): =
*Notice that the gate side of the drain perimeter is not included, as this is not considered a part of the side-wall
Similarly, the drain area and perimeter of the PMOS transistor are found

33. Wire capacitance Cw can also be calculated
drain area and perimeter of the PMOS transistor
Wire capacitance Cw can also be calculated
This physical information can be combined with the approximations derived above to come up with an estimation of CL using Table 3-5

37. Assignment-5 (Due date: 22/09/14
Multiply each dimension in the layout by 8 (eight) so that channel length is 2 um now and other dimensions also change. Find the propagation delay at the output of first inverter using SPICE simulation and compare it with the one obtained by finding CL, Req, Keq, etcetra using analytical expressions (as taught in the class).

38. Propagation Delay

39. CMOS Inverter Propagation Delay Approach 1

40. CMOS Inverter Propagation Delay Approach 2

41. ? *Cgd that couples i/p to o/p even before transistor is ON
Transient Response
? *Cgd that couples i/p to o/p even before transistor is ON
*Overshoots result in delay
Vin
tp = (tpLH+tpHL)/2
Vout
tp = 0.69 CL (Reqn+Reqp)/2
tpHL
tpLH

42. Delay as a function of VDD
optimize/manipulate delay
*CLM ignored here
VDD>> VTn + VDSATn/2
Delay independent of supply

43. Design for Performance
Keep capacitances small
Increase transistor sizes
watch out for self-loading!
Increase VDD (????)
- (oxide breakdown, hot electron effects)
- (energy-performance tradeoff)

44. Device Sizing Cint=SCref Req=Rref /S -PMOS wider: Rn=Rp,
tpLH=tpHL, symmetrical VTC,
Noise margin
-Delay can be smaller if
PMOS is small (else
tpHL degrades)
Device Sizing
(for fixed load)
Cint=SCref
Req=Rref /S
Self-loading effect:
Intrinsic capacitances
dominate
Slow further improvement
in delay
*Increasing transistor
size -> silicon area increases

45. Optimum NMOS/PMOS ratio
tpLH
tpHL
while widening the PMOS improves the tpLH of the inverter by increasing the charging current, it also degrades the tpHL by cause of a larger parasitic capacitance tp
How to derive optimum size ?
b = Wp/Wn
Fig. 5.18

46. Inverter Sizing

47. Finding Optimal Sizing ratio β
β=(W/L)p / (W/L)n
Assumed that WP = 2WN
same pull-up and pull-down currents
approx. equal resistances RN = RP
approx. equal rise tpLH and fall tpHL delays (symmetrical VTC)
doesn’t imply minimum propagation delay
If symmetry and Noise margins are not important then it is
possible to speed up inverter by reducing PMOS width.
(widening PMOS improves tPLH by increasing charging current, but it
degrades tPHL by causing larger parasitic capacitance)
A transistor ratio is required that optimizes propagation delay
of the inverter

48. Optimal Sizing ratio β …..
Out
CL1 CL
CL1 is the load capacitance of first gate
CL1=(Cdp1 + Cdn1) + (Cgp2 + Cgn2)+ CW
When β=(W/L)p / (W/L)n is applied (all other transistor parameters also scale by the same factor)
Cdp1 ≈ βCdn1 and Cgp2 ≈ βCgn2
so that CL1= (1+β)(Cdn1 + Cgn2)+ CW
from tp = 0.69 CL (Reqn+Reqp)/2

49. Optimal Sizing ratio β …..
where
The optimum value of β is found by setting ∂tp/∂β=0
Eqn. 5.26
If the wiring capacitance dominates, larger values of β should be used.
Smaller device sizes yield faster designs at the expense of
Symmetry and noise margin

50. Consider again our standard design example
Consider again our standard design example. From the values of the equivalent resistances (Table 3.3), we find that a ratio β of 2.4 (= 31 kW / 13 kW) would yield a symmetrical transient response. Eq. (5.26) now predicts that the device ratio for an optimal performance should equal 1.6. These results are verified in Figure 5.18, which plots the simulated propagation delay as a function of the transistor ratio b. The graph clearly illustrates how a changing β trades off between tpLH and tpHL. The optimum point occurs around β = 1.9,

51. Inverter Chain In Out CL If CL is given:
How many stages are needed to minimize the delay?
How to size the inverters?
May need some additional constraints.

52. Inverter Delay Minimum length devices, L=0.25mm
Assume that for WP = 2WN =2W
same pull-up and pull-down currents
approx. equal resistances RN = RP
approx. equal rise tpLH and fall tpHL delays
Analyze as an RC network 2W W
Delay (D):
tpHL = (ln 2) RNCL
tpLH = (ln 2) RPCL
Load for the next stage:

53. Inverter with Load CP = 2Cunit 2W W Cint CL CN = Cunit
Delay 2W W
Cint CL
Load
CN = Cunit
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)

55. How transistor sizing impacts the performance of a gate ?
sizing factor S, which relates the transistor sizes of our inverter to a reference gate—typically a minimum-sized inverter
tp0=0.69 ReqCint is independent of sizing of gate; and is determined purely by technology and inverter layout
Making S infinitely large yields the maximum obtainable performance gain, eliminating the impact of any external load, and reducing the delay to the intrinsic one.
S larger than Cext/Cint produce similar result at the cost of extra silicon area.

56. Delay Formula
*Inverter delay as a function of load capacitance and input capacitance
Cint = gCg with g  1 for most submicron technologies
f = Cext/Cg effective fanout :Cout/Cin
tp0 = 0.69ReqCint

57. Apply to Inverter Chain
Cg1 and CL are given In
Out CL 1 2 N
tp = tp1 + tp2 + …+ tpN
delay expression for j-th inverter stage
Total delay of the chain

58. Optimal Tapering for Given N
--Delay equation has N - 1 unknowns, Cg2 – Cg,N
--Minimum delay can be found by finding N - 1 partial -derivatives and equating them to zero ; ∂tp/∂Cg,j = 0
--Result: Cg,j+1/Cg,j = Cg,j /Cg,j-1 with j=2 to N [Eqn. 1]
--For example: j=2 gives Cg3/Cg2 = Cg2/Cg1
--Or Optimum Size of each stage is the geometric mean of two neighbors
this means that each inverter is sized up by the same factor ‘f ’ with respect to the preceding gate
each stage has the same effective fanout (Cout/Cin)
each stage has the same delay

59. Optimum Delay and Number of Stages
When each stage is sized by f and has same eff. fanout Fj=F :
Effective fanout of each stage ‘F’:
Where f is sizing factor
Minimum path delay through the chain

60. Example In
Out
CL= 8 C1 C1
Problem: Find the optimum sizes of all the inverters in this chain
so that the delay is minimum.

61. Example In
Out
CL= 8 C1 1 f f2 C1
CL/C1 has to be evenly distributed across N = 3 stages:

62. Buffer Design - Size the inverters Consider tp0=1 - Find delay 1 64 1

63. Buffer Design
N f tp
2 8 18
3 4 15 1 64 1 8 64 1 4 16 64 1 64
22.6
2.8 8

64. Power Dissipation

65. Where Does Power Go in CMOS?

66. Dynamic Power Dissipation
Vin
Vout C L
Vdd
Energy/transition = C
* V 2 L dd
Power = Energy/transition *
f = C
* V 2
* f L dd
Not a function of transistor sizes!
Need to reduce C
, V
, and f
to reduce power. L dd

67. Short Circuit Currents

68. Leakage Sub-threshold current one of most compelling issues
in low-energy circuit design!

69. Reverse-Biased Diode LeakageN p +
Reverse Leakage Current - V dd
GATE

70. Static Power Consumption
Wasted energy …
Should be avoided in almost all cases.

71. Principles for Power Reduction
Prime choice: Reduce voltage!
Recent years have seen an acceleration in supply voltage reduction
Design at very low voltages still open question (0.6 … 0.9 V by 2010!)
Reduce switching activity
Reduce physical capacitance

72. Impact of Technology Scaling

73. Goals of Technology Scaling
Make things cheaper:
Want to sell more functions (transistors) per chip for the same money
Build same products cheaper, sell the same part for less money
Price of a transistor has to be reduced
But also want to be faster, smaller, lower power

74. Technology Scaling Goals of scaling the dimensions by 30%:
Reduce gate delay by 30% (increase operating frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power 43% increase in frequency
Die size used to increase by 14% per generation
Technology generation spans 2-3 years

75. Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
186
177
171
160
130
106 90
Max mP power [W]
1.4
1.2
6-7
180
1999
1.7
2000
14.9
-3.6
11-3
3.5-2
Max frequency [GHz],Local-Global
2.5
2.3
2.1
2.4
2.0
Bat. power [W] 10
9-10 9 8 7
Wiring levels
Supply [V] 30 40 60
Technology node [nm]
2014
2011
2008
2004
2001
Year of Introduction
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

76. Technology Evolution (1999)

77. Technology Scaling (3) Propagation Delay tp decreases by 13%/year
50% every 5 years!
Propagation Delay

78. Technology Scaling Models

79. Scaling Relationships for Long Channel Devices

80. Transistor Scaling (velocity-saturated devices)