1. March 2006 Saeid Nooshabadi saeid@unsw.edu.au
ELEC2041 Microprocessors and Interfacing Lecture 5: Programmer’s Model of Microprocessors
March 2006
Saeid Nooshabadi

2. Programmer’s Model of a Microprocessor
Overview
Programmer’s Model of a Microprocessor
Address Space
Registers
Instruction Set
Fetch – Decode – Execute Cycle
Programmer’s Model of ARM 7TDMI
Translation of C to ASM

3. Recall: Pre-Requisite
Computers and Computing (e.g. COMP1011 & COMP1021)
C- Language Programming
The von Neumann model: memory/I-O/processing
The instruction set and execution cycle;
Registers and address spaces
An instruction set: operations and addressing modes
An expanded model of a computer: mass storage and I/O
The layered model of a computer: from gate- to user-level

4. Review: What is Subject about?
Application (Netscape)
ELEC2041
Operating
Compiler
System
(Windows XP)
Software
Assembler
Instruction Set
Architecture
Hardware
Processor
Memory
I/O system
Datapath & Control
Digital Design
Circuit Design
transistors
Coordination of many levels of abstraction

5. Review:Programming Levels of Representation
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
High Level Language Program (e.g., C)
ldr r0 , [r2, #0]
ldr r1 , [r2, #4]
str r1 , [r2, #0]
str r0 , [r2, #4]
Compiler
Assembly Language Program (e.g. ARM)
ELEC2041
Assembler
Machine Language Program (ARM)
Machine Interpretation
Control Signal Specification
ALUOP[0:3] <= InstReg[9:11] & MASK

6. Review: 5 Classic Components of a Computer
Network/Bus
Control
Datapath
Memory
Processor
Input
Output
Control
Datapath
Memory
Processor
Input
Output
ALU
Registers

7. An Expanded View of the Memory Systems
Cache is handled by hardware
Virtual memory is handled by and Operating System
Programmer sees only one memory and the registers
Processor
Control
Hard disk
(Virtual
Memory)
Main
Memory
2nd Cache
Datapath
Cache
Register
Slowest
Speed:
Fastest
Biggest
Size:
Smallest
Lowest
Cost:
Highest

8. Registers Small and fast memory inside the processor From memory
Load data from memory (Hold Data)
Store memory addresses (Hold Addresses)
Hold computation Operands and Results
Store back to memory
There are other specialized registers as well which are not visible to the programmer
32-bit ALU
Data: 32 bits
Register file
ARM has 16 Register:
r0 - r15, (each 32 bits)
From memory
Selectors:4 bits
In ARM r15 (pc) is
the program counter.
It points to the
instructions
in memory

9. Fetch Decode Execute Cycle
Instruction
Fetch
Decode
Operand
Execute
Result
Store
Next
Obtain instruction from program storage
Processor
Determine required actions
Input
Control
Memory
Locate and obtain operand data
Datapath
Output
Compute result value or status
ALU
Registers
Deposit results in storage for later use
Determine successor instruction

10. The Programmer’s Model of a Microcomputer
Instruction Set:
ldr r0 , [r2, #0]
add r2, r3, r4
Memory:
ldr r0 , [r2, #0] add r2, r3, r4 B
AEF0
Registers:
r0 - r3, pc
Memory mapped I/O
input
output
Addressing Modes:
ldr r12, [r1,#0]
mov r1 , r3
How to access data in registers and memory? i.e. how to determine and specify the data address in registers and memory
Programmer’s
Model

11. Memory Address Space (ARM 7TDMI)
230 = address space size in words
4 x 230 = address space size in bytes = 4GBytes
A word (4 bytes in memory)
Since 1980 almost every
machine uses addresses
to level of 8-bits (bytes)
Binary Contents
Addresses E
add r2, r3, r4
interpretations
instruction 0x E
sub r2, r5, r6 0x
instruction E
ldr r0, [r2] 0x
instruction
0x C 0x
Data 20hex = 3210
Same as variable
value
Same as variable

12. 16 Visible Registers (ARM 7TDMI)
They will be covered later
In ARM pc is the program counter.
It points to (contains the address of ) the instructions being fetched from memory.

13. Instruction Set (ARM 7TDMI)
Set of instruction that a processor can execute
Instruction Categories
Data Processing or Computational (Logical and Arithmetic
Load/Store (Memory Access: or transferring data between memory and registers)
Control Flow (Jump and Branch)
Floating Point
coprocessor
Memory Management
Special
Registers

14. Data Processing Instructions
Registers
Data Processing Instructions:
operate ONLY on registers
store result ONLY on registers
Category: Arithmetic, Logical, Data movement
Examples:
mov r1, r2 ; r1  r2
add r1, r2, r3 ; r1  r2 + r3
and r3, r3, r4 ; r3  r3 AND r4
All will be covered in detail later

15. Memory Access Instructions
Transfer data from a memory address to a register (load instructions)
Transfer data from a register to a memory address (store instructions)
Examples:
ldr r1, [r2] ; r1  mem[r2]
Address of memory location is in register r2
str r1, [r3] ; r1  mem[r3]
Address of memory location is in register r3
All will be covered in detail later

16. Control Flow Instructions
Generally next Instructions are fetched from Sequential addresses in Mem
Some Instructions cause fetch of next instruction from non sequential addresses in Mem (Control flow or branch instructions)
Examples:
br there E
add r2, r3, r4
instruction 0x E
sub r2, r5, r6 0x
instruction E
ldr r0, [r2] 0x
instruction
EA000004
br 0x
0x C
instruction E
add r2, r5, r5
instruction 0x
All will be covered in detail later

17. What’s this stuff good for? GameBoy!
Nidendo Micro GameBoy
The Micro, which began shipping September 2005, is easily the smallest member of Nintendo's hit GameBoy family.
The device is true to its name, measuring just 4 inches long by 2 inches deep and 0.68 inches thick
The GameBoy Micro is smaller than a deck of cards yet packs gaming power.
Nintendo says it has about the same power of previous GameBoy models despite its diminutive size.
It includes a 2-inch color LCD and buttons for both game control and menu selection. Nintendo also markets a variety of face plates to change to look of the device.
Powerd by ARM Processor
USD100

18. Computers In the News!
ARM7 and Nucleus RTOS on Tour with Paul McCartney
The Clair iO mastering processor (designed with an ARM7 core from Lake Technology Limited, Sydney, Australia) has been used in tours featuring Paul McCartney and other top artists.
The Clair iO is a 2-input, 6-output loudspeaker controller that employs 40-bit floating point DSP processing for a wholly innovative approach to live sound.
The iO’s innovative design is unique in its wireless network capability. The Nucleus Real-Time Operating System (RTOS) was used to develop a wireless DSP loudspeaker controller used by audio engineers to control live sound quality and management in concert arenas
Within the Clair iO processor, Nucleus acts as the communications link between the various host controllers on the Ethernet control side and the DSP processors, which manipulate the audio, on the other side. The iO processor is designed so that the ARM processor running the RTOS is separated from the DSP function.

19. ELEC2041 Reading Materials (#2/2)
Textbooks:
Main references for lecture material:
Steve Furber: ARM System on-chip 2nd Ed, Addison-Wesley, 2000, ISBN: We use chapters 2, 3, 5 and 6, 8, 9, 10, & 11
Additional references for lectures and labs:
David Patterson and John Hennessy: Computer Organisation & Design: The HW/SW Interface," 2nd Ed Relevant chapters are, 3, 4 & 8
Waldron, John: Introduction to RISC Assembly Language, Addison-Wesley Publishing, 1999, ISBN:
C-Programming
Brian Kernighan & Dennis Ritchie: The C Programming Language, 2nd Ed., Prentice Hall, 1988, ISBN:

20. ELEC2041 Laboratory Schedule
Monday: 09:00 – 11:00 EE233
Monday: 12:00 – 14:00 EE233
Tuesday: 15:00 – 17:00 EE233
Thursday: 09:00 – 11:00 EE233
Thursday: 12:00 – 14:00 EE233
Thursday: 15:00 – 17:00 EE233
Friday: 12:00 – 14:00 EE233
Friday: 15:00 – 17:00 EE233
You will be only allowed into the lab class that you are enrolled in. No exception allowed.
All Lab Classes Start from Week #3
There is a Possibility of Starting Special Open Access labs
Wednesday : 17:00 – 19:00 EE233
Thursday : 17:00 – 19:00 EE233
Not assessed
It is for those who need a bit of extra time

21. With xxxx being the group number, eg group_ea01, group_ee01
Laboratory Groups
Linux Lab Group Account
Day Time Group User Name
Monday: 09:00 – 11:00 ea01 – ea15
Monday: 12:00 – 14:00 eb01 – eb15
Tuesday: 15:00 – 17:00 ec01 – ec15
Thursday: 09:00 – 11:00 ed01 – ed15
Thursday: 12:00 – 14:00 ee01 – ee15
Thursday: 15:00 – 17:00 ef01 – ef15
Friday: 12:00 – 14:00 eg01 – eg15
Friday: 15:00 – 17:00 eh01 – eh15
PASSWORD: group_xxxx
With xxxx being the group number,
eg group_ea01, group_ee01
You must change your password the first time you log in.

22. Laboratory Format In group of two partners
You choose your partner in Sign Up Class (Week #3 for all classes) . It CANNOT be changed later
You will get a group Linux Account
No formal report to hand in
You are assessed based on a system of checkpoints
Assessors mark you check points
Lab Demonstrators help you with the lab
Assemble, link and run your program using the GNU Tools. Show your working program to the Laboratory Assessor.
Checkpoint 3: Signature:

23. All Tools included in the Companion CD-ROM
ELEC2041 Software
Edit Utility Tools
Enable creation of C or assembly source programs for ARM Processor on a Linux Platform
GNU ARM Cross Compiler and Assembler Tools:
Enable Translation by Compilation, Assembly, and Linking of source programs into ARM object programs; Executable and Linking Format (ELF)
GNU ARM Source Level Debugger
Enables simulation of ARM ELF programs while referencing back to the source code.
Komodo Integrated Debugger
Enables downloading of ARM ELF code into the target ARM Processor on DSLMU Development Board
Enables Execution and debugging of the downloaded program on the target processor on DSLMU Development Board
All Tools included in the Companion CD-ROM

24. Laboratory Documentation
Written Extensively
They Server as:
Lecture Notes
Tutorials
AND Practical exercise
Careful Reading Enables you to:
Understand the Subject material
Do tutorial practice
AND get practical experience
DO TAKE THEM VERY SERIOUS!

25. Sample Assembly Program
C statement: k = k - 2
0x80
0x84
0x88
0x8C
0x90
E3A02094
mov r2, #0x94
Instruction
(Data proc.)
E3A05002
mov r5, #2 E
ldr r0, [r2] 0x
(Mem Access)
Data 20hex = 3210
Binary Contents E
sub r0, r0, r5 E
str r0, [r2]
(Data proc)
0x94
r x94
0x94 r 2 r2 r0
0x94
0x20
0x20 r0 r5
0x2
0x1E - r2 r0
0x94
0x1E
0x E
Location for variable k

26. Compilation
How to turn notation programmers prefer into notation computer understands?
Program to translate C statements into Assembly Language instructions; called a compiler
Example: compile by hand this C code: a = b + c; d = a - e;
Easy: add r1, r2, r3 sub r4, r5, r6
Big Idea: compiler translates notation from 1 level of abstraction to lower level

27. Instructions are all 32 bits Instruction Categories
Conclusion
ARM has bit registers
Instructions are all 32 bits
Instruction Categories
Data Processing or Computational (Logical and Arithmetic
Load/Store (Memory Access: or transferring data between memory and registers)
Control Flow (Jump and Branch)
Access to memory is only through ldr and str instructions