1. SOC & VLSI
PROCESSOR
Harold Yu Fu Lin
Sumana Kumar
04/28/2011

2. SOC & VLSI Project : Network on chip Team : Processor team
Group : Sumana Kumar
Harold Yu Fu Lin
Guidance : Dr. Levitan
Dr. Jones

3. SOC & VLSI: Network on chip
Block diagram from kona.ee.pitt.edu/socvlsi

4. SOC & VLSI: Network on chip
Introduction :
This project involved the development of a multi-processor network
This team was involved in :
1. Developing a buffer
2. Compiling and simulating the ARM cortexM0 processor
3. Generating the ram.bin files for the memory

5. SOC & VLSI: Network on chip
Synthesis of the Cortexm0 processor
DC synthesis was performed
Synthesis successful at 130MHz
Fig : Screen shot showing the slack is 0

6. SOC & VLSI: Network on chip
Place and route of cortexm0
Encounter tool was used
Fig : screenshot showing the post route timing report. No errors and no violations encontered

7. SOC & VLSI
Size :
536.9um * 541.3um

8. SOC & VLSI: Network on chip
Modelsim was used for simulating and testing the Cortexmo processor
Post PR simulation runs at 100 MHz

9. SOC & VLSI: Network on chip
ARM compiler
This was used to generate the ram.bin files required for the memory
Hello world program was first first converted into a ram.bin file from a .c file
This was modified to read ‘Hell word’ to test and prove the working of the generated ram.bin files

10. SOC & VLSI: Network on chip

11. SOC & VLSI: Network on Chip
Compiler Program : Explained in a few other slides.

12. SOC & VLSI
THANK YOU