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MSP432 ARM Timer Programming

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Presentation on theme: "MSP432 ARM Timer Programming"— Presentation transcript:

1 MSP432 ARM Timer Programming
Chapter 5 MSP432 ARM Timer Programming

2 A 3-bit Counter

3 An 8-bit up-counter stages

4 An 8-bit down-counter stages

5 Counting Events Using a Counter

6 Using Counter as a Timer

7 Capturing

8 System Tick Timer Internal Structure

9 STCTRL (System Tick Control)

10 System Tick Counting

11 STRVR vs. STCVR

12 System Tick Timer Internal Structure

13 Timer32 Registers Offset Acronym Register Name Type Reset Value 00H
T32LOAD1 Timer 1 Load Register RW 04H T32VALUE1 Timer 1 Current Value Register R FFFFFFFFH 08H T32CONTROL1 Timer 1 Timer Control Register 20H 0CH T32INTCLR1 Timer 1 Interrupt Clear Register W - 10H T32RIS1 Timer 1 Raw Interrupt Status Register 14H T32MIS1 Timer 1 Interrupt Status Register 18H T32BGLOAD1 Timer 1 Background Load Register T32LOAD2 Timer 2 Load Register 24H T32VALUE2 Timer 2 Current Value Register 28H T32CONTROL2 Timer 2 Timer Control Register 2CH T32INTCLR2 Timer 2 Interrupt Clear Register 30H T32RIS2 Timer 2 Raw Interrupt Status Register 34H T32MIS2 Timer 2 Interrupt Status Register 38H T32BGLOAD2 Timer 2 Background Load Register 0H

14 T32CONTROLxRegister

15 Counting in Free-Running Mode vs. Periodic Mode

16 T32RIS Register

17 T32LOAD vs. T32VALUE

18 The Timer32 Prescaler

19 Timer_A Simplified Diagram

20 A more detailed diagram of Timer_A

21 TAxR register

22 TAxCTL register

23 TAxCTL register bit Name Description TAIFG Timer_A Interrupt Flag
TAIFG Timer_A Interrupt Flag 0: Timer did not overflow 1: Timer overflowed 1 TAIE Timer_A Interrupt Enable (0: Disabled, 1: Enabled) 2 TACLR Timer_A Clear 4-5 MC Mode Control: 00: Stop mode: timer is halted 01: Up mode: Timer counts up to TAxCCR0 10: Continuous mode: Timer counts up to 0xFFFF 11: Up/down mode: Timer counts up to TAxCCR0 then down to 0. 6-7 ID Input divider: These bits select the divider for the input clock: 00: divide by 1 01: divide by 2 10: divide by 4 11: divide by 8 8-9 TASSEL Timer_A clock Source Select: These bits select the Timer_A clock source: 00: TAxCLK (external clock): The timer uses external clock which is fed to the PM_TAxCLK pin. 01: ACLK (internal clock) 10: SMCLK (internal clock) 11: INCLK

24 TAxCCRn Registers and TAxCCTLn Flags

25 TAxCCRn Register

26 TAxCCTLn Register

27 TAxCCTLn Register (Table 17-6 of the chip manual)
bit Name Description 15-14 CM Capture mode 00: No capture 01: Capture on rising edge 10: Capture on falling edge 11: Capture on both rising and falling edges 13-12 CCIS Capture/compare input select. These its select the TAxCCR0 input signal: 00: CCIxA 01: CCIxB 10: GND 11: VCC 11 SCS Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0: Asynchronous capture 1: Synchronous capture

28 TAxCCTLn Register (Table 17-6 of the chip manual) (Cont.)
bit Name Description 10 SCCI Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be read via this bit. 8 CAP Capture mode 0: Compare mode 1: Capture mode 7-5 OUTMOD Output mode. Modes 2, 3, 6, and 7 are not useful for TAxCCR0 because EQUx = EQU0 000: OUT bit value 001: Set 010: Toggle/reset 011: Set/reset 100: Toggle 101: Reset 110: Toggle/set 111: Reset/set

29 TAxCCTLn Register (Table 17-6 of the chip manual) (Cont.)
bit Name Description 4 CCIE Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0: Interrupt disabled 1: Interrupt enabled 3 CCI Capture/compare input. The selected input signal can be read by this bit. 2 OUT Output. For output mode 0, this bit directly controls the state of the output. 0: Output low 1: Output high 1 COV Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0: No capture overflow occurred 1: Capture overflow occurred CCIFG Capture/compare interrupt flag 0: No interrupt pending 1: interrupt pending

30 TAxEXn Register

31 Counting in Up Mode

32 Clock in Timer_A

33 Continuous mode

34 Input Edge Time Capturing

35 TAxCCTLn Register

36 TAxCCTLn Register (Table 17-6 of the chip manual)
bit Name Description 15-14 CM Capture mode 00: No capture 01: Capture on rising edge 10: Capture on falling edge 11: Capture on both rising and falling edges 13-12 CCIS Capture/compare input select. These its select the TAxCCR0 input signal: 00: CCIxA 01: CCIxB 10: GND 11: VCC 11 SCS Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0: Asynchronous capture 1: Synchronous capture

37 TAxCCTLn Register (Table 17-6 of the chip manual) (Cont.)
bit Name Description 10 SCCI Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be read via this bit. 8 CAP Capture mode 0: Compare mode 1: Capture mode 7-5 OUTMOD Output mode. Modes 2, 3, 6, and 7 are not useful for TAxCCR0 because EQUx = EQU0 000: OUT bit value 001: Set 010: Toggle/reset 011: Set/reset 100: Toggle 101: Reset 110: Toggle/set 111: Reset/set

38 TAxCCTLn Register (Table 17-6 of the chip manual) (Cont.)
bit Name Description 4 CCIE Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0: Interrupt disabled 1: Interrupt enabled 3 CCI Capture/compare input. The selected input signal can be read by this bit. 2 OUT Output. For output mode 0, this bit directly controls the state of the output. 0: Output low 1: Output high 1 COV Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0: No capture overflow occurred 1: Capture overflow occurred CCIFG Capture/compare interrupt flag 0: No interrupt pending 1: interrupt pending

39 Choosing the Capture Edge
CM Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both edges

40 Port pin assignement of Timer_A
TA0.0 P7.3 TA1.0 P8.0 TA2.0 P8.1 TA3.0 P10.4 TA0.1 P2.4 TA1.1 P7.7 TA2.1 P5.6 TA3.1 P10.5 TA0.2 P2.5 TA1.2 P7.6 TA2.2 P5.7 TA3.2 P8.2 TA0.3 P2.6 TA1.3 P7.5 TA2.3 P6.6 TA3.3 P9.2 TA0.4 P2.7 TA1.4 P7.4 TA2.4 P6.7 TA3.4 P9.3

41 Measuring Period and Pulse Width

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