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Machine Instructions and Programs contd:
Course code: 10CS46 UNIT-2 Machine Instructions and Programs contd: Engineered for Tomorrow Prepared by : Alpana Dahiya and Akshatha P S Department :Computer Science Date :
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Outline Addressing Modes Assembly Language
Basic Input Output Operations Stacks and Queues Subroutines Additional Instructions Encoding of Machine Instructions 7 Hours
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ADDRESSING MODES The different ways in which the location of an operand is specified in an instruction is called as Addressing mode. Generic Addressing Modes: Immediate mode Register mode Absolute mode Indirect mode Index mode Base with index Base with index and offset Relative mode Auto-increment mode Auto-decrement mode
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Implementation of Variables and Constants
The value can be changed as needed using the appropriate instructions. There are 2 accessing modes to access the variables. They are • Register Mode • Absolute Mode Register Mode: The operand is the contents of the processor register. The name (address) of the register is given in the instruction. Absolute Mode (Direct Mode): The operand is in a memory location. The address of this location is given explicitly in the instruction.
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The operand is specified in the instruction itself
Constants Address and data constants can be represented using: Immediate Addressing Mode: The operand is specified in the instruction itself Move 200immediate, R0 Move #200, R0
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Indirection and pointers
Indirect mode – the Effective address of the operand is the contents of a register or memory location whose address appears in the instruction The register of memory location that contains the address of an operand is called a pointer Analogy of treasure hunt Instead of finding the treasure, we find the address where we find the treasure By changing the contents of register R1 or location A in the following figure, the same add instruction fetches different operands to add to register R0.
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Figure 2.11. Indirect addressing.
Add (R1),R0 Add (A),R0 Main memory B Operand A B R1 B Register B Operand (a) Through a general-purpose register (b) Through a memory location Figure Indirect addressing.
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Indirect addressing logic for the program of adding n numbers using loop
Contents Move N,R1 Move #NUM1,R2 Initialization Clear R0 LOOP Add (R2),R0 Add #4,R2 Decrement R1 Branch>0 LOOP Move R0,SUM Figure Use of indirect addressing in the program of Figure 2.10.
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Indexing and Arrays Index mode – the effective address of the operand is generated by adding a constant value to the contents of a register. Index register X(Ri): EA = X + [Ri] The constant X may be given either as an explicit number or as a symbolic name representing a numerical value. If X is shorter than a word, sign-extension is needed.
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Indexing and Arrays In general, the Index mode facilitates access to an operand whose location is defined relative to a reference point within the data structure in which the operand appears. Several variations: (Ri, Rj): EA = [Ri] + [Rj] X(Ri, Rj): EA = X + [Ri] + [Rj]
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Indexed addressing Figure 2.13. Indexed addressing. 20 = offset
Add 20(R1),R2 1000 1000 R1 20 = offset 1020 Operand (a) Offset is given as a constant Add (R1),R2 1000 20 R1 20 = offset 1020 Operand (b) Offset is in the index register Figure Indexed addressing.
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• Figure 2.14. A list of students' marks. N n LIST Student ID LIST + 4
Test 1 Student 1 LIST + 8 Test 2 LIST + 12 Test 3 LIST + 16 Student ID Test 1 Student 2 Test 2 Test 3 • Figure A list of students' marks.
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Note: contents of R0, which is used as indexed register, are not changed when it is used in indexed addressing mode to access test scores. Contents of R0 change only in last Add instruction, to move from one student record to the next Move #LIST,R0 Clear R1 Clear R2 Clear R3 Move N,R4 LOOP Add 4(R0),R1 Add 8(R0),R2 A d d 12(R0),R3 Add #16,R0 Decrement R4 Branch>0 LOOP Move R1,SUM1 Move R2,SUM2 Move R3,SUM3 Figure Indexed addressing used in accessing test scores in the list in Figure 2.14.
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Indexed addressing contd…
Several variations of the basic form of indexed addressing provide efficient access to memory operands A second register may be used to contain the offset X, called as based indexed addressing mode Denoted as ( Ri, Rj ) Effective address is the sum of contents of Ri and Rj Second register is called base register. Provides more flexibility to the user Eg., suppose, in the previous example, instead of only 3 items, each student record contain a large no of items, say k We can replace the three Add instructions by a single instruction inside a second loop
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Indexed addressing contd…
Several variations of the basic form of indexed addressing provide efficient access to memory operands A second register may be used to contain the offset X, called as based indexed addressing mode Denoted as ( Ri, Rj ) Effective address is the sum of contents of Ri and Rj Second register is called base register. Provides more flexibility to the user Eg., suppose, in the previous example, instead of only 3 items, each student record contain a large no of items, say k We can replace the three Add instructions by a single instruction inside a second loop
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Solution
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Indexed addressing mode contd..
based indexed addressing mode with offset Uses two registers plus a constant X( Ri, Rj ) - Effective address is the sum of the constant X and the contents of registers Ri and Rj This mode implements 3-Dimensional array
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Relative addressing Eg., Branch>0 LOOP
Till now for index mode, registers we used are general purpose registers A useful variation of this is to use Program Counter PC instead of a general purpose register X(PC) – to address a memory location that is X bytes away from the location presently pointed to by the program counter Relative mode- the effective address is determined by the index mode using the program counter in place of the general-purpose register Ri. MOST common use is to specify the target address in branch instructions Eg., Branch>0 LOOP If branch condition is true, the program execution goes to branch target location identified by name LOOP Can compute this location by specifying it as an offset from the current value of the program counter. Since branch target address can be either before or after the branch instruction, the offset is given as a signed number
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Example for relative addressing mode
Contents Assume 4 instructions starting from LOOP are located at memory locations 1000,1004,1008 & 1012. Updated contents at the time branch target address is generated is to branch to location LOOP(1000), the offset value needed is X = -16 Move N,R1 Move #NUM1,R2 Initialization Clear R0 LOOP Add (R2),R0 Add #4,R2 Decrement R1 Branch>0 LOOP Move R0,SUM
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Auto increment addressing logic for the program of adding n numbers using loop
Move N,R1 Move #NUM1,R2 Initialization Clear R0 LOOP Add (R2)+,R0 Decrement R1 Branch>0 LOOP Move R0,SUM Figure The Autoincrement addressing mode used in the program of Figure 2.12.
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Autodecrement mode The contents of a register specified in the instruction are first automatically decremented and are then used as the effective address of the operand Denoted by –(Ri) Operands are accessed in descending address order. The way the autoincrement and autodecrement modes are specified in very useful when implementing an important data structure called a stack. Always we can use two instructions to perform the functionality of autoincrement and autodecrement mode
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ASSEMBLY LANGUAGE Machine instructions are represented by patterns of 0s and 1s Such patterns are awkward to deal when discussing or preparing programs Hence, usage of symbolic names to represent the patterns Such symbolic acronyms( short forms) is called as mnemonics A complete set of symbolic names and rules for their use constitute a programming language, referred to as assembly language The set of rules for using the symbolic names is called as syntax of the language
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Assembly language Programs written in an assembly language can be automatically translated into a sequence of machine instructions by a program called an assembler. The user program in its original form is called as source program The assembled machine language program is called object program The assembly language for a given computer may or may not be case sensitive
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Assembly language A move instruction is written as
MOVE R0,SUM The mnemonic MOVE represents the binary pattern, or OP code, for the operation performed by the instruction The assembler translates this mnemonic into the binary OP code that the computer understands OP-code followed by at least one blank space character Then the information that specifies the operands is given In above example , source operand is in register R0 Followed by specification of the destination operand – separated from source operand by a comma, with no intervening blanks In above example destination operand is in memory location that has its binary address represented by name SUM
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Assembly language Since there are several possible addressing modes for specifying operand locations, the assembly language must indicate which mode is being used. # sign indicates immediate operand ( eg., ADD #5,R3) In some assembly languages the immediate addr mode is intended in the OP-code mnemonic( eg., ADDI 5,R3) Indirect addressing mode is usually specified by putting parentheses around the name denoting pointed operand. If number 5 is to be placed in a memory location whose address is held in register R2, it is specified as MOVE #5,(R2)
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Assembler directives In addition to providing mechanisms for representing instructions in a program, the assembly language allows programmer to specify other information needed to translate the source program to object program Eg., if name SUM is used to represent value 200, it can be conveyed to assembler as SUM EQU 200 This statement will not appear in the object program.. Rather informs the assembler that the name SUM is to be replaced by the value 200 Such statements are called as assembler directives Eg., ORIGIN – where in the memory should the data/instruction block that follows be placed DATAWORD – load the location with specified value RETURN – identifies the point at which execution of the program must be terminated. Assembler returns control to OS by inserting an appropriate machine instruction
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Figure 2.18. Assembly language representation
Memory Addressing address or data label Op eration information 100 Move N,R1 104 Move #NUM1,R2 108 Clear R0 Assembler SUM EQU 200 LOOP 112 Add (R2),R0 directives ORIGIN 204 116 Add #4,R2 N D A T A W ORD 100 120 Decrement R1 NUM1 RESER VE 400 124 Branch>0 LOOP ORIGIN 100 128 Move R0,SUM Statements ST AR T MO VE N,R1 132 that generate MO VE #NUM1,R2 machine CLR R0 instructions LOOP ADD (R2),R0 ADD #4,R2 SUM 200 DEC R1 N 204 100 BGTZ LOOP NUM1 208 MO VE R0,SUM NUM2 212 Assembler RETURN directives END ST AR T NUM n 604 Fig2.17.Memory arrangement for program in Fig 2.12. Figure Assembly language representation
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Memory Addressing Any statement that results in instructions or data being placed in memory location may be given a memory address label. Label is assigned the value equal to the address of that location address or data lab el Op eration information Assem bler directiv es SUM EQU 200 ORIGIN 204 N D A T A W ORD 100 NUM1 RESER VE 400 ORIGIN 100 Statements that ST AR T MO VE N,R1 generate MO VE #NUM1,R2 mac hine CLR R0 instructions LOOP ADD (R2),R0 ADD #4,R2 DEC R1 BGTZ LOOP MO VE R0,SUM Assem bler directiv es RETURN END ST AR T Figure Assembly language representation for the program in Figure 2.17.
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contd…. Most assembly languages require statements in a source program to be written in the form Label Operation Operand(s) Comment Label – is optional and is associated with memory address where the machine language instruction or the data items are stored Operation field contains the OP-code mnemonic of the desired instruction or assembler directive Operand field contains addressing information for accessing one or more operands, depending on the type of instruction Comment field is ignored by the assembler program Used for documentation purposes
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Assembly and execution of programs
ASSEMBLER replaces All symbols denoting operations and addressing modes with binary codes All names and labels with their actual values. In a branch instruction, branch target is not replaced by actual address. Usually it uses relative addressing mode. Assembler computes branch offset, and puts into the machine instruction The assembler keeps track of all names and the numerical values that correspond to them in a symbol table When a name appears a second time, it is replaced with its value from the table. A problem arises if some name appears before it is given a value. Eg., forward branching. Solution is to scan through the program twice – once to collect the values of all names and second time to substitute values for all names from symbol table. Such an assembler is called as TWO-PASS ASSEMBLER
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Assembly and execution of programs
Assembler stores object program on a magnetic disk The object program must be loaded into memory before it is executed A utility program called loader does this. For this loader must already be in memory Loader must know the length of the program and the address in the memory where it will be stored Assembler usually places this info in a header preceding the object code When the object program begins execution, it proceeds to completion unless there are errors. To help debugging, system software usually includes a debugger program
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Number notations Can use either decimal, or binary or hexadecimal notation Eg., ADD #93, R1 This is in decimal In binary – ADD #% ,R1 Here % tells that we are using a binary number In hexadecimal – ADD #$5D, R1 Here $ denotes the usage of hexadecimal
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BASIC INPUT/OUTPUT OPERATIONS
Till now we have assumed that the data operated in stored in memory already. Now, let’s see how data transfer takes place between computer and outside world The I/O operations are very important and the way they are done can significantly affect the performance of the computer The rate of data transfer from the keyboard to a computer is limited by the typing speed of the user Few characters per second The rate of output transfers from the computer is determined by the rate at which characters can be transmitted over the link between the computer and display device. Typically several thousand characters per second Both are much slower than the speed of processor Can execute many millions of instructions per second Hence need for the mechanisms to synchronize the transfer of data between them.
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Solution to speed disparity
On output, the processor sends the first character and then waits for a signal from the display that character has been received Then it sends the second character and so on For input, the processor waits for a signal indicating that a character key has been struck and that its code is available in some buffer register associated with keyboard Then only will processor proceed to read the code
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DATAIN/DATAOUT – buffer registers
SIN/SOUT – status control flags The striking of a key on keyboard does not automatically cause the corresponding character to be displayed on the screen! One block of instructions in I/O program causes the character to be transferred to processor and another block of instructions will cause the character to be displayed on the screen
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How data is read? The technique used is called program – controlled I/O Striking a key stores the corresponding character code in a 8-bit buffer register called DATAIN. To inform the processor that a valid character is in DATAIN, a status control flag SIN is set to 1. A program monitors SIN, and when SIN is set to 1, the processor reads the contents of DATAIN. When the character is transferred to the processor, SIN is automatically cleared to 0. When a second character is read, SIN is again set to 1 and the process repeats
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How data is displayed? A buffer register DATAOUT and status control flag SOUT is used. When SOUT is 1, display is ready to receive a character Under the control of a program, ( hence program – controlled I/O), the processor monitors SOUT and when SOUT is set to 1, the processor transfers a character code to DATAOUT The transfer of character to DATAOUT clears SOUT to 0. When the display is ready to receive a second character, again SOUT is set to 1. SIN , SOUT , DATAIN, DATAOUT are part of circuitry called as device interface, connected to processor through bus
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Programs for I/O Assume that SIN is set to 0 initially and SOUT is set to 1. This initialization is performed by device control circuits How to refer to the buffers DATAIN and DATAOUT? Many computers use arrangement called as memory-mapped I/O Some memory address values are used to refer to peripheral device buffer registers such as DATAIN and DATAOUT Thus no special instructions required to access the contents of these registers Eg., Movebyte DATAIN, R1 moves the contents of keyboard character buffer DATAIN to R1 Similarly, Movebyte R1, DATAOUT The status flags SIN and SOUT are automatically cleared when the buffer registers are referenced Movebyte signifies that the operand is a byte, not a word
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Programs for I/O It is common to include SIN and SOUT in device status registers, which have distinct memory addresses Assume that the status registers are INSTATUS and OUTSTATUS respectively for input and output Also assume that SIN and SOUT are referred by bit3 in the registers. Read operation READWAIT Testbit #3, INSTATUS Branch=0 READWAIT Movebyte DATAIN,R1 Write operation WRITEWAIT Testbit #3,OUTSTATUS Branch=0 WRITEWAIT Movebyte R1,DATAOUT
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Mo v e #LOC,R0 Initialize p oin ter register R0 to p oin t to the address of the first lo cation in memory where the c haracters are to b e stored. READ T estBit #3,INST A TUS W ait for a c haracter to b e en tered Branc h=0 READ in the k eyb oard buffer D A T AIN. Mo v eByte D A T AIN,(R0) T ransfer the c haracter from D A T AIN in to the memory (this clears SIN to 0). ECHO T estBit #3,OUTST A TUS W ait for the displa y to b ecome ready . Branc h=0 ECHO Mo v eByte (R0),D A T A OUT Mo v e the c haracter just read to the displa y buffer register (this clears SOUT to 0). Compare #CR,(R0)+ Chec k if the c haracter just read is CR (carriage return). If it is not CR, then Branch 0 READ branc h bac k and read another c haracter. Also, incremen t the p oin ter to store the next c haracter. Figure A program that reads a line of characters and displays it.
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STACKS and QUEUES Stacks mainly used to organize control and information linkage between main program and the subroutine A stack is a list of elements, usually words or bytes, with the accessing restriction that elements can be added or removed at one end of the list only. This end is called as the top of stack The other end is called as bottom Hence also called as pushdown stack Eg., a pile of trays in a cafetaria Storage mechanism is also referred by LIFO ( Last-in-First-Out) Push – put an element on top of stack Pop – remove an element from top of stack
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• Stack pointer register SP Current - 28 top element 17 739 Stack • Bottom BOTTOM 43 element Normal practice is stack grows in the direction of decreasing memory addresses • Stack pointer(SP) – is a processor register used to keep track of the address of the top element of stack 2 k - 1 Figure A stack of words in the memory.
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Push and Pop operations on Stack
Stack pointer keeps track of the address of the top of stack To Push an element Subtract #4,SP Move NEWITEM,(SP) To Pop an element Move (SP),ITEM Add #4,SP If processor support autoincrement and autodecrement Push Move NEWITEM,-(SP) Pop Move (SP)+,ITEM
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Stacks contd… Care has to be taken that stack is not popped when empty and pushed when full Usage of Compare instruction Compare src,dst [dst] – [src] and affect flags accordingly eg/., BOTTOM – at addres 2000 Till location 1500
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SAFEPOP Compare #2000,SP Chec k to see if the stac k p oin ter con
tains Branc h > EMPTYERR OR an address v alue greater than 2000. If it do es, the stac k is empt y . Branc h to the routine EMPTYERR OR for appropriate action. Mo v e (SP)+,ITEM Otherwise, p op the top of the stac k in to memory lo cation ITEM. (a) Routine for a safe pop operation SAFEPUSH Compare #1500,SP Chec k to see if the stac k p oin ter Branc h FULLERR OR con tains an address v alue equal to or less than 1500. If it do es, the stac k is full. Branc h to the routine FULLERR OR for appropriate action. Mo v e NEWITEM, – (SP) Otherwise, push the elemen t in memory lo cation NEWITEM on to the stac k. (b) Routine for a safe push operation Figure Checking for empty and full errors in pop and push operations.
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Queue – First In First Out List
Data elements are inserted in memory at the increasing order of memory addresses i.e., at the back of Queue. Data elements are retrieved from memory at the decreasing order of memory addresses i.e. from the front end of Queue. Operations such as QINSERT and QDELETE can be performed on a queue to insert and delete & element respectively. A Queue consisting of 6 elements may appear as follows:
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Difference between implementation of stacks and queues
One end of a stack is fixed ( bottom ), while the other end rises and falls as data are pushed and popped. Hence a single pointer is needed to point to the top of stack at any given time. A stack is assigned a fixed amount of space in memory. Queues Both ends of queue move to higher addresses as data are added at the back and removed from the front. So two pointers are needed to keep track of the two ends of the queue. Without further control, a queue would continuously move through the memory of a computer in the direction of higher addresses. One way to limit the queue to a fixed region in memory is to use a circular buffer.
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SUBROUTINES In a given program, it is many times needed to perform a particular subtask on different data values. Such a sub task is called as subroutine Eg., a subroutine to calculate sine function, or to sort a list of values in increasing or decreasing order One copy of the instructions that constitute subroutine is placed in the memory, and any program that requires the use of subroutine branches to its starting location. This branching to a subroutine is termed as calling the subroutine The instruction which performs this is Call instruction
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Subroutines - Linkage After a subroutine has been executed, the calling program must resume execution continuing immediately after the instruction that called the subroutine. This is performed by a Return instruction Since a subroutine may be called from different places, we need to make provision to return to appropriate location The location where the calling program resumes execution is the location pointed to by the updated PC while the Call instruction is being executed. Hence, need to save the contents of PC by Call instruction to enable correct return. The method in which computer calls and returns from subroutines is referred to as subroutine linkage method Simplest way is to save the return address in a specific location, which may be a register dedicated to perform this function Such a register is called as link register When the subroutine completes its task, the Return instruction returns to the calling program by branching indirectly through the link register
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Call instruction performs the following operations
Memory Memory location Calling program location Subroutine SUB 200 Call SUB 1000 first instruction 204 next instruction Return 1000 PC 204 Link 204 Call Return Call instruction performs the following operations Store the contents of PC in link register Branch to the target address specified by the instruction Return instruction performs the following operation i. Branch to the address contained in link register Figure Subroutine linkage using a link register.
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Subroutines - nesting and processor stack
Subroutine nesting – it’s a practice where in one subroutine calls another subroutine. In this case, the return address of the second call is also stored in link register, destroying its previous contents. Hence, need to save the contents of link register in some other location before calling another subroutine. Else the return address of first subroutine is lost Subroutine nesting can be carried out to any depth. Last subroutine that is called completes computations and returns to the subroutine which called it. Hence return addresses are generated and used in a last-in-first-out order. Hence return addresses can be pushed onto a stack. Many processors do this automatically as one of the operations performed by call instruction A special pointer called stack pointer, points to a stack called processor stack. the call instruction pushes the contents of the PC onto the processor stack and loads the subroutine address into the PC. The return instruction pops the return address from the processor stack into the PC
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Subroutines - parameter passing
When calling a subroutine, a program must provide to the subroutine the parameters, (operands or their addresses), to be used in the computation The subroutine returns other parameters ( the results of computation) back. This exchange of information between calling program and subroutine is called as parameter passing Can be done in several ways Can place the parameters in registers or memory locations Placing in processor registers in highly efficient and straight forward No of parameters that can be passed is limited by the number of general purpose registers available The parameters may also be placed on processor stack. Highly flexible and can handle a large no of parameters
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Addition of N numbers in a loop using subroutines
Addition of N numbers in a loop using subroutines. Parameters are passed through registers Calling program Mo v e N,R1 R1 serv es as a coun ter. Mo v e #NUM1,R2 R2 p oints to the list. Call LIST ADD Call subroutine. Mo v e R0,SUM Sa v e result. . . . Subroutine LIST ADD Clear R0 Initialize sum to 0. LOOP Add (R2)+,R0 Add en try from list. Decremen t R1 Branc h > LOOP Return Return to calling program. Figure Program of Figure 2.16 written as a subroutine; parameters passed through registers.
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Program to add a list on n numbers written as a subroutine.
Parameters are passed through processor stack NOTE : parameter passing either by pass by value or pass by reference n – is passed by value (actual value is passed) NUM1 – passed by reference. address is passed ( not the actual entries of the list but the address of first element is passed Figure Program of Figure 2.16 written as a subroutine; parameters passed on the stack.
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Subroutines – Stack Frame
The locations which will be used by the subroutine on stack for private work, constituting a private work space for the subroutine, which is created at the time the subroutine is entered and freed up when the subroutine returns control to the calling program, is called as stack frame. Can also allocate space for local memory variables
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Stack frames In addition to stack pointer, it is useful to have another additional pointer register, called frame pointer (FP) The local variables are local to the subroutine, hence can be allocated space in stack frame associated with the subroutine FP points to the location just above the return address Contents of FP remain fixed throughout the execution of subroutine
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Access parameters using index addr mode.
Move FP,-(SP) Move SP,FP SP saved [R1] (stack pointer) saved [R0] localvar3 Subtract #12,SP localvar2 localvar1 Stack frame FP (frame pointer) saved [FP] for called Return address subroutine param1 Access parameters using index addr mode. 8(FP), 12(FP) Local variables can be accessed using addresses -4(FP), -8(FP) param2 param3 param4 Old TOS (top-of-stack) The calling program is responsible for removing parameters from stack frame, some of which may be results passed back by the subroutine Figure A subroutine stack frame example.
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Stack frames for nested subroutines
Stack is a proper data structure for holding return addresses when subroutines are nested Complete stack frames for nested subroutines build up on the processor stack Saved contents of FP in the current stack frame are the frame pointer contents for the stack frame of the subroutine that called the current subroutine
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Memory lo cation Instructions Commen ts Main program . . . 2000 Mo v e P ARAM2, – (SP) Place parameters on stack. 2004 Mo v e P ARAM1, – (SP) 2008 Call SUB1 Figure shows only flow of control and data between subroutines. Not the actual computations 2012 Mo v e (SP),RESUL T Store result. 2016 Add #8,SP Restore stack lev el. 2020 next instruction . . . First subroutine 2100 SUB1 Mo v e FP – , (SP) Sa v e frame p oin ter register. 2104 Mo v e SP ,FP Load the frame p oin ter. 2108 Mo v eMultiple R0 – R3, – (SP) Sa v e registers. 2112 Mo v e 8(FP),R0 Get first parameter. Mo v e 12(FP),R1 Get second parameter. . . . Mo v e P ARAM3, – (SP) Place a parameter on stack. 2160 Call SUB2 2164 Mo v e (SP)+,R2 P op SUB2 result in to R2. . . . Mo v e R3,8(FP) Place answ er on stack. Mo v eMultiple (SP)+,R0 – R3 Restore registers. Mo v e (SP)+,FP Restore frame p oin ter register. Return Return to Main program. Second subroutine 3000 SUB2 Mo v e FP – , (SP) Sa v e frame p oin ter register. Mo v e SP ,FP Load the frame p oin ter. Mo v eMultiple R0 – R1, – (SP) Sa v e registers R0 and R1. Mo v e 8(FP),R0 Get the parameter. . . . Mo v e R1,8(FP) Place SUB2 result on stack. Mo v eMultiple (SP)+,R0 – R1 Restore registers R0 and R1. Mo v e (SP)+,FP Restore frame p oin ter register. Return Return to Subroutine 1. Figure Nested subroutines.
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Figure 2.29. Stack frames for Figure 2.28.
[R1] from SUB1 [R0] from SUB1 Stack frame FP [FP] from SUB1 for second 2164 subroutine param3 [R3] from Main [R2] from Main [R1] from Main Stack [R0] from Main frame for FP [FP] from Main first subroutine 2012 param1 param2 Old TOS Figure Stack frames for Figure 2.28.
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ADDITIONAL INSTRUCTIONS
Instructions so far Move Load Store Clear Add Subtract Increment Decrement Branch Testbit Compare Call Return Even this small set of instructions has a number of redundancies Eg., Load and Store instructions can be replaced by a single Move instruction Increment by Add and Decrement by Subtract instruction Clear by a Move ( moving zero )
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Additional instructions
Logic instructions Not Complement all the bits in destination operand Not R0 ( complement all bits of R0) Can get 2’s complement representation of a negative number Not R0 ( R0 contains, say 3) Add #1,R0 Can get 2’s complement of a number by a single instruction Negate R0 Bitwise And , Or Performs and & or operations bitwise And #$FF000000,R0 Problem : write a program which checks whether an entered 4letter word contains Z in the beginning.
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Additional instructions
Answer And $#FF000000, R0 Compare #$5A000000,R Branch=0 YES And instruction is often used in practical programming tasks where all bits of an operand except for some specified field are to be cleared to zero Problem: Write program to clear the bits b10 to b31 in a 4 byte word
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Additional instructions – shift and rotate instructions
Shift instructions For general operands we use logical shifts For signed numbers, we use arithmetic shifts ( to preserve the sign of the number) Logical Shifts 2 instructions – for left shift and for right shift LShiftL count, destination LShiftR count, destination Count can be given either as immediate operand or given inside a processor register Vacated positions are filled with zeros The bits shifted out are passed through the Carry flag, C, and then dropped
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C R0 . . . before: 1 1 1 1 1 after: . . . 1 1 1 1 1 (a) Logical shift left LShiftL #2,R0 R0 C . . . before: 1 1 1 1 1 after: 1 1 1 . . . 1 (b) Logical shift r ight LShiftR #2,R0 R0 C . . . before: 1 1 1 1 . . . after: 1 1 1 1 1 1 (c) Ar ithmetic shift r ight AShiftR #2,R0 Figure Logical and arithmetic shift instructions.
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Additional instructions – Shift and Rotate instructions
Digit packing 2 decimal digits represented in ASCII are located in memory at byte locations LOC and LOC + 1 Represent each of these digits in 4-bit BCD and store in a single byte location PACKED (the result is said to be in packed-BCD format) Hint: rightmost 4 bits of the ASCII code for a decimal digit correspond to the BCD code for the digit
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Mo v e #LOC,R0 R0 points to data. Mo v eByte (R0)+,R1 Load first b yte in to R1. LShiftL #4,R1 Shift left b y 4 bit p ositions. Mo v eByte (R0),R2 Load second b yte in to R2. And #$F,R2 Eliminate high-order bits. Or R1,R2 Concatenate the BCD digits. Mo v eByte R2,PACKED Store the result. Figure A routine that packs two BCD digits.
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Additional instructions – Shift and Rotate instructions
Arithmetic Shifts Shifting a number one bit left is same as multiplying the number by 2 Overflow may occur Shifting right is equivalent to dividing the number by 2 Reminder is lost On a right shift sign-bit must be repeated as the fill in bit for the vacated position, main difference between Arithmetic shift and logical shift
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Additional instructions – Shift and Rotate instructions
4 in number Rotate left without Carry – RotateL Rotate left with Carry – RotateLC Rotate right without Carry – RotateR Rotate right with Carry - RotateRC
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C R0 before: 1 1 1 . . . 1 1 after: 1 1 1 . . . 1 1 1 (a) Rotate left without carry RotateL #2,R0 C R0 before: 1 1 1 . . . 1 1 after: 1 1 1 . . . 1 1 (b) Rotate left with carry RotateLC #2,R0 R0 C . . . before: 1 1 1 1 1 . . . after: 1 1 1 1 1 1 (c) Rotate r ight without carr y RotateR #2,R0 R0 C . . . before: 1 1 1 1 1 after: 1 1 1 1 . . . 1 (d) Rotate r ight with carr y RotateRC #2,R0 Figure Rotate instructions.
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Additional instructions – Shift and Rotate instructions
Multiplication and Division Multiply Ri,Rj Product can be as large as 2n bits for 2 n-bit numbers Answer will not necessarily fit in Rj Lower order bits in Rj, higher order bits in Rj+1 Some systems provide Divide Ri ,Rj Rj/Ri and quotient in Rj May place remainder in Rj+1 Computers which do not have divide and multiply instructions can implement same using basic instructions like add, subtract, shift and rotate
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ENCODING OF MACHINE INSTRUCTIONS
Till now we have not used acronyms for instructions because they are specific to a particular processor in market ( eg., we used Move instead of MOV ) To be executed, an instruction must be encoded in a compact binary pattern. Such encoded instructions are properly referred to as machine instructions The instructions that use symbolic names and acronyms are called as assembly language instructions, which are converted to machine instructions using assembler program
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Encoding of machine instructions
The type of operation to be performed and the type of operands used is specified using an encoded binary pattern referred to as the OP code for the given instruction Suppose 8 bits are assigned for OP code to specify upto 256 different instructions If we assume that word length is 32-bits and if we want to fit an entire instruction into a single memory word, then we are left with 24 bits to specify rest of the information Eg., Add R1,R2 has to specify the registers R1 and R2, in addition to the OP code If system has 16 registers, then 4 bits are required to identify each register and some additional bits to specify that we are using register addressing mode
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Encoding of machine instructions
Move 24(R0) ,R5 16 bits to denote OP code, 2 registers, some bits to express that source operand uses index addressing mode and that index value is 24 Suppose 3 bits are used to specify addressing mode We need 6 bits – to denote the chosen addressing mode for both source and destination operands 32 – ( 16+6) = 10 bits left to give the index value ( signed number ) Eg., LShiftR #2,R0 Move #$3A, R1 how many bits left to specify immediate value?
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Encoding of machine instructions
Branch>0 LOOP Here 8 bits for OP code. How many bits for Branch OFFSET? What is the limit for the branch target address with respect to branch insrtuction? Jump instruction - uses Absolute or Register Indirect mode to specify branch target
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Encoding of machine instructions
CISC processors use instructions that are complex and require more than a single word to specify the instruction Consider instruction Add LOC,R2 Here 8 bits for OP code, 10 bits for addr mode and specifying the register, remaining 14 bits cannot hold a 32-bit address of the absolute addressing mode Hence we need to go either for multiple word instruction Or Register Indirect Load address of LOC to R3 Add (R3),R2
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Figure 2.39. Encoding instructions into 32-bit words.
8 7 7 10 OP code Source Dest Other info (a) One-word instruction OP code Source Dest Other info Memory address/Immediate operand (b) Two-word instruction OP code R i R j R k Other info (c) Three-operand instruction Figure Encoding instructions into 32-bit words.
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Encoding of machine instructions
How to load 32-bit address to register? One way is to use indexed addressing mode to load the address into register ( for this need to place the address in a memory location close to the program) Other option is to use Logical and Shift instructions – passing the address by parts The restriction that the instruction must fit in a single word ( 32 bit here ) is the style of RISC machines Places a restriction that all manipulation of data contained only in processor registers Move (R3) ,R1 Add R1,R2
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