1. Interrupt
Source:
under

2. Response to an interrupt
When an interrupt occurs the following happens:
The current instruction completes execution.
The PC is saved on the stack (ie; the address of the next instruction).
The address of the ISR (i.e., Interrupt vector) for the interrupt is loaded into the PC.
ISR: Interrupt Service Routine

3. five interrupt sources
The 8051 has five interrupt sources.
Two external interrupts: pins INTO-bar and INT1-bar (port 3 pin 2 and port 3 pin 3)
Two internal interrupts: timer 0 overflow & timer 1 overflow
The serial port: when a byte has been transmitted or when a byte is received

5. The interrupt enable register (an SFR)
An interrupt can be disabled and enabled.
On power-up or reset all interrupts are disabled.
* To enable interrupts we set the appropriate bits in the interrupt enable SFR.
Symbol
Bit Number
Description EA 7
Enable/disable all interrupts. If this bit is cleared all interrupts are disabled. If it is set each interrupt source is individually enabled or disabled by setting or clearing the appropriate enable bit, as detailed below. -- 6 5 ES 4
Enable/disable serial port interrupts (set to enable, clear to disable).
ET1 3
Enable/disable timer 1 overflow interrupt (set to enable, clear to disable).
EX1 2
Enable/disable external 1 interrupt (set to enable, clear to disable).
ET0 1
Enable/disable timer 0 overflow interrupt (set to enable, clear to disable).
EX0
Enable/disable external 0 interrupt (set to enable, clear to disable).
SETB EA SETB ET0
CLR EX1

6. Interrupt Flags The 1st bit of TCON register Interrupt Flag Location
External 0
IE0
TCON.1
External 1
IE1
TCON.3
Timer 0
TF0
TCON.5
Timer 1
TF1
TCON.7
Serial Port Receive RI
SCON.0
Serial Port Transmit TI
SCON.1
The 1st bit of TCON register

7. Interrupt Vectors The WR-bar line is used for starting a conversion.
When an interrupt in the 8051 occurs, the vector address, as shown above, is loaded into the PC.
Interrupt
Flag
Vector
System reset
RST
0000H
External interrupt 0
IE0
0003H
Timer 0
TF0
000BH
External interrupt 1
IE1
0013H
Timer 1
TF1
001BH
Serial port
RI or TI
0023H
The WR-bar line is used for starting a conversion.
Clearing this line resets the internal successive-approximation register and the 8-bit shift register.
When the line is set conversion begins.

8. Scenario of Interrupting

9. External Interrupts Interrupt pins:
the INT0-bar (P3.2) & INT1-bar (P3.3) pins
Trigering conditions:
a low-level or negative edge on the interrupt pins
Choice of the triggering condition:
the IT0 and IT1 bits (in the TCON register)
The interrupt flags:
IE0 and IE1 (in the TCON register);
0 for low-level triggering, 1 for negative edge triggering
Sampling rate
 The external interrupt pins are sampled (ie; tested) once every machine cycle.
Note: Machine cycle = 1 us for 12 MHz clock rate