1. CPRE 583 Reconfigurable Computing Instructor: Dr. Phillip Jones
Lecture 7: 9/15/2010 (Common VHDL Mistakes: “It works perfect in simulation, but not in the hardware!” )
Instructor: Dr. Phillip Jones
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA

2. Announcements/Reminders
MP1/HW1 Due midnight tonight
MP2: Make sure to get started by Thursday (tomorrow
HW2: Delayed Thur/Fri release, due date will be appropriated adjusted.
Mini literary survey
PowerPoint tree due: Fri 9/17 by class, so try to have to me by 9/16 night. My current plan is to summarize some of the classes findings during class.
Final 5-10 page write up on your tree due: Fri 9/24 midnight.

3. Literary Survey
Start with searching for papers from on IEEE Xplorer:
Advanced Search (Full Text & Meta data)
Find popular cross references for each area
For each area try to identify 1 good survey papers
For each area
Identify 2-3 core Problems/issues
For each problem identify 2-3 Approaches for addressing
For each approach identify 1-2 papers that Implement the approach.

4. Literary Survey: Example Structure
Hardware Accelerated
Bioinformatics P1 P2 P3 A1 A2 A3 A1 A2 A1 A2 I1 I1 I2 I1 I1 I1 I1 I2 I1
5-10 page write up on your survey tree

5. Common Questions

6. Common Questions

7. Overview Common VHDL mistakes What you should learn
What are the ~6 common mistakes
How to identify these mistakes
How to fix these mistakes

8. My design works in simulation, but not in hardware!!
Clocked and non-clock processes common issues.
Clean Statemachine design, using best know practices
Common Mistakes pdf document

9. Clocked vs. non-clock processes
Non-clocked process
(clock is NOT in the sensitivity list)
Clocked process
(clock is ONLY in the sensitivity list)
process (clk)
begin
-- check for rising edge of the clk
if(clk’event and clk = ‘1’) then
-- initialize all driven signals during reset
if(reset = ‘1’) then
a_out <= x”00”;
data_out <= x”00”;
else
if (sel = ‘1’) then
a_out <= a;
data_out <= my_data;
end if;
end process;
process (sel, a, my_data)
begin
-- default all driven signals
a_out <= x”00”;
data_out <= x”00”;
if (sel = ‘1’) then
a_out <= a;
data_out <= my_data;
end if;
end process;

10. State Machine Structure
-- Assign STATE to next state
process (clk)
begin
-- check for rising edge of the clk
if(clk’event and clk = ‘1’) then
-- initialize all driven signals during reset
if(reset = ‘1’) then
STATE <= S1;
else
STATE <= Next_STATE;
end if;
end process;
-- Compute next state
process (STATE, x)
begin
-- defaults
next_state <= STATE;
case STATE is
when S1 =>
if(x = ‘0’) then
Next_STATE <= S1;
else
Next_STATE <= S2;
end if;
when S2 =>
Next_State <= S1;
end process;
No memory!!!!
Has memory
(e.g. flip-flops)

11. Manage Registers/Counters
process (clk)
begin
if(clk’event and clk = ‘1’) then
-- initialize all driven signals during reset
if(reset = ‘1’) then
store_x_reg <= x”00”;
counter_1 <= x“00”;
else
-- update registers and counters
if(update_reg) then
store_x_reg <= new_val;
end if;
if(update_count) then
counter_1 <= new_count;
end process;
These are memory elements
(e.g. flip-flops)

12. Good papers on state machine design
FSM “good practices” paper (Note: inVerilog)
The Fundamentals of Efficient Synthesizable Finite State Machine (2002)
Synthesizable Finite State Machine Design Techniques (2003)

13. Common Mistakes in more detail
See Common VHDL mistakes pdf on course web

14. Common Mistakes in more detail

15. Common Mistakes in more detail

16. Common Mistakes in more detail

17. Common Mistakes in more detail

18. Common Mistakes in more detail

19. Common Mistakes in more detail

20. Common Mistakes in more detail

21. Common Mistakes in more detail

22. Common Mistakes in more detail

23. Common Mistakes in more detail

24. Common Mistakes in more detail

25. Common Mistakes in more detail

26. Common Mistakes in more detail

27. Common Mistakes in more detail
Correct Example of a counter

28. Common Mistakes in more detail

29. MP2 overview

30. MP2 overview

31. MP2 overview

32. MP2 overview

33. MP2 overview

34. Next Class VHDL -> FPGA, or
Short History of Reconfigurable computing

35. Questions/Comments/Concerns