1. Digital Logic Design 1st Exam Solution

2. 1. Calculate 12-7 and 7-12 by using 2’s complement binary number.
Sol：以 5 bits 表示
1210 = (2’s complement)
710 = (2’s complement)
(a) = 12 + (-7) (b) 7 – 12 = 7 + (-12)
= = -5

3. 2. Complete the truth table, Boolean equation, and the
2. Complete the truth table, Boolean equation, and the logic circuit for a full adder. (不需簡化)
Truth table A B
Cin S
Cout
A B Cin
Cout S
0 0 0
0 1 0
1 0 0
1 1 0
0 0 1
0 1 1
0 1
1 1 1
0 0
0 1
1 0
1 1

4. 3. Given F(A, B, C, D) = Σ m(1, 3, 5, 7, 9, 15)+ Σ d(2, 13, 14)
(a) Complete the truth table 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0
0 1 0 1 X 1 X

5. (b) write down the canonical SOP form (Boolean
(b) write down the canonical SOP form (Boolean equation), and draw the logic circuit
F =
A’B’C’D
+A’B’CD
+A’BC’D
+A’BCD
+AB’C’D
+ABCD
A B C D F
0 0 0
0 1 0 1 X

6. (c) minimize F by using k-map method, and draw the logic circuit
A B C D F
0 0 0
0 1 0 1 X AB CD 1 X 00 01 11 10
F=A’D+BD+C’D

7. (d) Convert the circuit into NAND-NAND
F=A’D+BD+C’D

8. 1 X ABCD = 0010 ABCD = 1101 F = A’D+BD+C’D F = A’D+BD+C’D = 0’0+00+1’0
(e) in the circuit of (c), what is the value of F, if ABCD=0010? What is the value of F, if ABCD=1101?
ABCD = 0010
ABCD = 1101
F = A’D+BD+C’D
F = A’D+BD+C’D
= 0’0+00+1’0
= 1’1+10+0’1
= 0
= 1 AB CD 1 X 00 01 11 10

9. 4. Minimize F(A, B, C, D) = Σ m(1, 3, 5, 7, 9, 15)+ Σ d(2, 13, 14) by using Quine-McClausky method
0 0 0
0 1 0 1 X
(a) I II
III 1 2 3 5 9 7 13 14 15
0001
0010
0011
0101
1001
0111
1101
1110
1111
00-1
0--1
--01
-1-1 *
0-01 *
-001 *
0001
001-
0-11
01-1
-101
1-01
-111
11-1
111- * *

10.
(2, 3)
(14, 15)
(1, 3, 5, 7)
(1, 5, 9, 13)
(5, 7, 13, 15)
001-
111-
0--1
--01
-1-1 X X X X X X X X X X X X
F = A’D+C’D+BD

11. F (b) Implement the logic circuit for F using a 4:1 multiplexer
A B C D F
0 0 0
0 1 0 1 X D D
C’D D / C

12. 5. Implement a 32:1 multiplexer by using four
5. Implement a 32:1 multiplexer by using four 8:1 multiplexers and a 4:1 multiplexer. ～
8 : 1 7 24 31
C D E ～ ～ 8 15 16 23
C D E ～
8 : 1 1 2 3
A B
4 : 1 F ～ ～

13. 6. Complete the waveform for the circuit. Assume
6. Complete the waveform for the circuit. Assume the inverter has two units, the NAND gate has 1 unit, and the AND gate has 1 unit in delay.