1. FLIPPED CLASSROOM ACTIVITY CONSTRUCTOR

2. Table of Contents SECTION SLIDE # 5 11 20 ABOUT YOU 3
OUT-OF-CLASS SEGMENT 5
IN-CLASS SEGMENT 11
EVALUATION 20
COMMUNITY BUILDING

3. About you
I Dr.Veena M.B. working as a Associate professor, ECE Department, BMSCE, Bangalore. The topic in which I want to design a Flipped classroom is on Verilog HDL

4. Dr. Veena M.B Introduction to Hardware Description Language
Verilog HDL
ELECTRONICS
1st YEAR PG STUDENTS IN ELECTRONICS ENGINEERING
ECE, BMSCE Bengaluru-19

5. Out-of-class Segment
This section helps you design the Out-of-Class segment of
Flipped Classroom Strategy.

6. Out-of-class Activity Design -1
Learning Objective(s) of Out-of-Class Activity
At the end of watching the videos student should be able to
Understand the principle behind Hardware description language (understand Level)
Use of Modern Electronic design process(Apply Level)
Acquire a knowledge on hardware simulation (understand level)
Key Concept(s) to be covered
Electronic Design
Hardware Description language(Verilog)

7. Out-of-class Activity Design - 2
Main Video Source URL
License of Video
CC-BY-SA (reuse allowed)
Mapping Concept to Video Source
CONCEPT
VIDEO SEGMENT
DURATION
(in min)
Introduction of HDL
V1 - 0:00 – 10:00
10:00
V2 - 10:08 – 19:36
09:18
V3 - 40:43 – 50:56
10:13
Verilog Basics
V4 - 00:00 – 9:41
09:41
TOTAL DURATION: 39min 12sec

8. Out-of-class Activity Design - 3
Aligning Assessment with Learning Objective
Learning
Objective
Assessment Strategy
Expected duration
(in min)
Additional Instructions (if any)
Understand the principle behind Hardware description language (understand Level)
Use of modern Electronic design process(Apply Level)
Acquire a knowledge on hardware simulation (understand level)
Q1.What is the main challenge for Modern electronic design.
Q2.How hardware description is different from software.
Q3. Discuss on the steps involved in hardware simulation
10 minutes
Watch V1 and then answer Q1
Watch V2 and then answer Q2
Watch V3 and then answer Q3.
Submission on time will be graded and also linked to the attendance.

9. Out-of-class Activity Design - 3
Aligning Assessment with Learning Objective
Learning Objective
Assessment Strategy
Expected Duration
(in min)
Additional Instructions (if any)
Explain the basic concepts of verilog HDL with their construct
Q1. Construct 16:1 Multiplexer using 4:1 Multiplexer with code
Q2. Write a behavior code for a D-FlipFlop
10 minutes
Watch V4 and then answer Q1 and Q2

10. Out-of-class Activity Design - 3
Aligning Assessment with Learning Objective
Learning Objective
Assessment Strategy
Expected Duration
(in min)
Additional Instructions (if any)
Apply the concept of Digital design to analyze the behavior of the circuit
Q1.How would you describe the behavior of the given circuit with output function.
10 minutes
Submit answers to all questions 3 hours before coming to class.
Total activity duration
30 minutes

11. In-class Segment
This section helps you design the in-class segment of Flipped Classroom Strategy.

12. In-class Activity Design -1
Learning Objective(s) of In-Class Activity
At the end of the class, students will be able to,
Develop real-life scenario problems understanding the principles of hardware description language (ANALYZE Level)
Implement Digital circuits using combinational & sequential logic (ANALYZE Level)
Key Concept(s) to be covered
Use of modern electronic design process for Real World Problem Solving.
Implementation using combinational & sequential logic .

13. In-class Activity Design -2
Active Learning activity(ies) that you plan to do
Real world problem solving using.
Think-Pair-Share
Concept clarification using.
Peer Instruction

14. In-class Activity Design -2
Peer Instruction Strategy – What Teacher Does
Teacher Poses an objective type problem
Q 1: A digital multiplexer is a combinational circuit that selects a) One digital information from several sources and transmits the selected one b) Many digital information and convert them into one c) Many decimal inputs and transmits the selected information d) None of the Mentioned

15. In-class Activity Design -2
Peer Instruction Strategy – What Teacher Does
Teacher Poses an objective type problem
 Q 2 A combinational circuit that selects one from many inputs a) Encoder b) Decoder c) Demultiplexer d) Multiplexer

16. In-class Activity Design -2
Peer Instruction Strategy – What Student Does
For each question they will first vote individually.
Then they will discuss with peers and come to consensus.
Listen to instructors explanation.

17. In-class Activity Design -2
TPS Strategy – What Instructor does
Instructor will give a problem to analyze, Design and Implement
Problem statement: Develop a verilog model that counts 16 clock cycles and produces a control signal, ctrl, that is 1 during every eighth and twelth cycle. Design a circuit for the same.

18. In-class Activity Design -2
TPS Strategy – What Instructor does
Think (~2 minutes)
Instruction: Assuming that initial count is zero for the counter and then creating a 3 bit register in order to store the count value, when it encounter 12th or 8th bit then control signal has to be enable high.
student will think individually and try to write a algorithm/code.

19. In-class Activity Design -2
TPS Strategy – What Instructor does
Pair (~5 minutes) Student forms a pair and Develops a Verilog code for the problem analyzed and discuss about code optimization with their neighbor. Here student will try to write an optimized code discuss with his neighbor and compare answers. Agree on one final answer. While students are pairing and discussing, instructor goes to 2~3 sections to see what they are doing.
CODE 1
module decoded_counter (C, CLR, Q);
input Clk, CLR;
output [3:0] Q;
reg [3:0] tmp;
Clk or posedge CLR)
    begin
      if (CLR)
        tmp = 4'b0000;
      else
        tmp = tmp + 1'b1;
      end
  assign Q = tmp;
assign ctrl = Q = = 4'b0111 ||Q = = 4'b1011;
end module
CODE 2
module counter (clk, clr, q);
parameter MAX_SQRT = 4,
MAX = (MAX_SQRT*MAX_SQRT);
Input clk, clr;
output [MAX_SQRT-1:0] q;
reg [MAX_SQRT-1:0] cnt;
(posedge clk or posedge clr)
begin
if (clr)
cnt <= 0;
else
cnt <= (cnt + 1) %MAX;
end
assign q = cnt;
end module

20. In-class Activity Design -2
TPS Strategy – What Instructor does
Share (~8 minutes)
Instructor asks a group to share their answer with class and see whether there are different answers. After sharing is done, instructor gives feedback on the correct optimised solution
Optimised Code
module decoded_counter ( output ctrl,input clk );
reg [3:0] count_value;
clk)
count_value <= count_value + 1;
assign ctrl = count_value = = 4'b0111 || count_value = = 4'b1011;
endmodule

21. In-class Activity Design -2
Justify why the above is an active learning strategy
In both the above strategies, students are required to go beyond mere listening and execution of prescribed steps. They are required to think deeply about the content they were familiarized in out-of-class and do higher order thinking.
There is also feedback provided by instructor summary.