1. Combinational Circuit Design
Presented by
K. Pandiaraj
Assistant Professor
ECE
Kalasalingam University

2. Logic Gates

3. Combinational Circuit Design
Design Procedure:
Determine required number of inputs and outputs from the specifications.
Derive the truth table for each of the outputs based on their relationships to the input.
Simplify the Boolean expression for each output. Use Karnaugh Maps or Boolean algebra.
Draw a logic diagram that represents the simplified Boolean expression. Verify the design by analysing or simulating the circuit.

5. HALF ADDER

6. FULL ADDER

9. Half Subtractor
Half Subtractor is used for subtracting one single bit binary digit from another single bit binary digit. The truth table of Half Subtractor is shown below.

10. Full Subtractor

11. Multiplexers A multiplexer has
N control inputs
2N data inputs
1 output
A multiplexer routes (or connects) the selected data input to the output.
The value of the control inputs determines the data input that is selected.

12. Multiplexer

13. Demultiplexers A demultiplexer has
N control inputs
1 data input
2N outputs
A demultiplexer routes (or connects) the data input to the selected output.
The value of the control inputs determines the output that is selected.
A demultiplexer performs the opposite function of a multiplexer.

14. Demultiplexers I W X Y Z A B W = A'.B'.I X = A.B'.I Y = A'.B.I
Out0 In S1 S0 I W X Y Z A B
Out1
Out2
Out3
W = A'.B'.I
X = A.B'.I
Y = A'.B.I
Z = A.B.I A B W X Y Z I 1

15. Decoders

16. Decoders
A decoder has
N inputs
2N outputs
A decoder selects one of 2N outputs by decoding the binary value on the N inputs.
The decoder generates all of the minterms of the N input variables.
Exactly one output will be active for each combination of the inputs.

17. Decoders W = A'.B' W B X = A.B' X Y A Y = A'.B Z Z = A.BI0 I1 A
Out0
Out1
Out2
Out3
W = A'.B'
X = A.B'
Y = A'.B
Z = A.B
msb
Active-high outputs A B W X Y Z 1

18. Decoders W = (A'.B')' W B X = (A.B')' X Y A Y = (A'.B)' Z Z = (A.B)'I0 I1 A
Out0
Out1
Out2
Out3
W = (A'.B')'
X = (A.B')'
Y = (A'.B)'
Z = (A.B)'
msb
Active-low outputs A B W X Y Z 1

19. Decoders
msb

20. Decoder with Enable W B X A Y Z Enable I0 I1 En Out0 high-level Out1x
enabled
disabled

21. Decoder with Enable W B X A Y Z Enable I0 I1 En Out0 low-level Out11 x
enabled
disabled

22. Encoders

23. Encoders An encoder has
2N inputs
N outputs
An encoder outputs the binary value of the selected (or active) input.
An encoder performs the inverse operation of a decoder.
Issues
What if more than one input is active?
What if no inputs are active?

24. Encoders D I0 C Z I1
Out0
Out1 Y B I2 A I3 A B C D Y Z 1

25. Priority Encoders
If more than one input is active, the higher-order input has priority over the lower-order input.
The higher value is encoded on the output
A valid indicator, d, is included to indicate whether or not the output is valid.
Output is invalid when no inputs are active
d = 0
Output is valid when at least one input is active
d = 1

26. Priority Encoders
msb
Valid bit

27. Digital Comparator
A magnitude digital comparator is a combinational circuit that compares two digital or binary numbers (consider A and B) and determines their relative magnitudes in order to find out whether one number is equal, less than or greater than the other digital number.
Three binary variables are used to indicate the outcome of the comparison as A>B, A<B, or A=B. The below figure shows the block diagram of a n-bit comparator which compares the two numbers of n- bit length and generates their relation between themselves.

28. Single Bit Magnitude Comparator

29. 2-Bit Comparator

30. 2-Bit Comparator

31. 2-Bit Comparator