1. The CMS pixel detector: Low Mass Design & Lessons Learned
Linear Collider Meeting
Vertex Detector Technology
CERN, Bld
5. August 2010
R. Horisberger, PSI

2. History on CMS Pixel System
Present pixel detector conceived in 1996 / 97 with:
focus on easy insertion/removal of pixel system
keep material budget low  achieved % X0/Layer (h=0)
use analog optolinks of strip APV readout  adaptation in geometry
keep optolinks at maximum radius  limit rad. damage
Operate at L =1034 at radii 7cm & 11cm  data rates, buffer size
rad. hard DMILL technology 0.8mm  2 ½ metal layers
5.5V supply
BiCMOS (was useful)
present pixel ROC architecture with :
1) Zero channel suppression (pixel hit discrimination)
2) Analog pulse height readout (~ 7-8 bit)
Readout : pixel address (5 clocks) + analog pulse height (1 clock)

3. Analog coded pixel readout
Overlap of 4160 pixel readouts
1 pixel hit
1 clock cycle:
analog pulse height
chip
header
5 clock cycles:
encode 13 bits of pixel address information.
col#
pix#
Present system: had to use analog optical link available !
Future sLHC system: digital bit stream through high speed link ! (add 1 ADC/ROC)

4. Column Drain Architecture
Time-stamp buffer
Depth: 12
data buffer
Depth: 32
marker bits indicate
start of new event
set
fast double
column OR
hit
data
column drain
mechanism
pixel unit cells: 2x80
sketch of a double column
double
column
pixels
32 data
buffers
12 time stamp
double column
interface
7.8mm
9.8mm
Transfer data rapidly to periphery and store for L1 latency ( ~3.4usec)

5. History of CMOS technologies
DMILL pixel ROC worked ! Yield: pixel defect <1%
1-5 pixel defect %
Translation DMILL ROC to 0.25um ROC with big financial & electrical benefits
DMILL m IBM Ratio
Wafer size ” ” ~2x (area)
Wafer cost [CHF] 12K K ~4x
Yield % (<5px def.) % (0 def.) ~3x
Total : ~ 24 x Cost benefits
Engineering run ~200K ~160k
Will the change from 0.25mm to 0.13mm give a similar benefit?
No ! um production wafers of same size (8”) are 250% more expensive
Engineering run ~ 2.5 times more expensive.

6. 250nm Pixel ROC IBM_PSI46 Chip modified to DMILL version
7900mm
Chip modified to DMILL version
- should have uniform address levels
- external Operation is same
Chip Internal Power Regulators
Column Drain Architecture
more timestamp & data buffers
8   32
now fit for r=4cm at L=1034
less power  28mW/pixel
smaller pixel area: 100m x 150m
Total # transistors : 1280 K
(DMILL 430K )
IBM_PSI46
9800mm

7. SLHC situation Track rates at L = 10 35 cm-2 sec-1
Technology already exists for SLHC tracking at radii > 20cm :
Silicon Pixels Detector
Performance of present pixels at SLHC?
LHC Rates
@10 34
r = 4cm
r = 7cm
r = 11cm
SLHC Rates
@10 34
r = 18cm
r = 30cm
r = 50cm

8. Rate tests of CMS Pixel Modules
High rate tests in X-ray box allows hit rates up to 300 MHz/cm2
Simulation of pixel read out chip (ROC) compares quite well with observed data loss
We can identify the data loss mechanisms
 finite data buffers
 readout times
For SEU studies and timewalk need to go to pion beam line at PSI
 150 MHz/cm2
 20nsec bunch structure
LHC (1034cm-2s-1): cm cm cm

9. Costs of a CMS Pixel Barrel Module
Cables (40cm) & TBM etc. 100 SFr
HDI (High Density Interconnect) 300 SFr
Sensor (DS, n+ in n-Si) SFr
Bump bonding SFr
16 Readout chips 0.25m 250 SFr
( DMILL: SFr )
Baseplate (SiN) SFr
Module of Area = 10cm2 Costs ~ 4700 SFr
Optical links, FED , FEC, Power supplies add +15%  ~550 SFr/cm2

10. Costing Speculations [CHF/cm2]
* = C4NP (IBM)
Pixel (now) Large pixels Macropixels MAPS CMOS+Sensor
Pixel Area mm mm2 1.5 mm
Sensor/ROC / / / / / 1
Tiling unit cm cm cm cm cm2
Bumping * *
Sensors ?(4)
ROC ?(3)
HDI
Cables
Baseplate
Pitchadjust (2)
Optical Link (1)
pxFED
Total ~ ~ ~ ~320?
~ 320 CHF/channel
~ 0.02 CHF/cm fine pitch trace
Yield speculations based on experience with DMILL SOI-wafers
Extra cost for anodic wafer bonding or SOI wafer growth

11. C4NP Low Cost Bumping Injection Molded Solder (IBM & Süss)
IMS Principle
Mold
IMS allows bump 75m size and pitch of 150m
200m thick wafers processed so far
Wafer costs (300mm) ~ 150 $

12. Material budget & Supplies
Material budget for 3 Layers at h = 0
Current Pixel Barrel System:
Bring power in = 4%
(On-Chip regulators,Al-wire)
Take power out = 29%
Cooling is material budget driver !
Low mass cooling and/or
Reduce power consumption !
X/X0 = 5.79% for 3 barrel pixel layers
 1.93% / layer
(ATLAS ~2.5%)

13. Power Issues of Tracker Readout
Current consumption: Analog: Strips  reduce noise
Pixels  speed (timewalk) ! !
Digital: Information processing (data flow)
CMS ROC: ID = 32mA no tracks
ID = 40mA at 40MHz/cm2 track rate
Reduce power by :
- Technology CMOS 0.25m  0.13m  Digital: local: YES global: NO
 Analog: NO W.I. 
on chip regulators
- Architecture choice Pixel ROC Power : ALICE mW/cm no
ATLAS mW/cm no
CMS* mW/cm yes
CMS mW/cm no
- Custom protocols TBM05 ~ 1/6 power of TBM02
abandon LVDS for 5cm distance  custom
protocol LCDS (Low Current Differential Swing)
The next SLHC tracker must be very cautious and careful with power consumption !

14. Power Dissipation of LHC Pixel ROC’s
ROC architecture and designs have considerable influence on power dissipation
3 chips in same 0.25m technology for same LHC environment
# Pixels
/ chip
Pixel area
[mm2]
Idig
[mA]
Iana
Power/ chi p
[mW]
Power/ pix el
Power density
[ mW/cm2 ]
ALICE
8192
21’250
150
300
810 99
466
ATLAS
2880
20’000 35 75
190 67
335
CMS
4160
15’000 32 24
121 29
194
CMS no on-chip regulators

15. Sensor Capacitance & Analog Power
Spice simulation of present CMSPIX front end with fixed timewalk (<25nsec)
Time walk is power driver not noise !
Current for 65 Mega Pixel
estimated 3D-pixel sensor capacitance
measured CMS pixel capacitance (n-pixel 100mm x 150mm, p-spray)

16. Power consequences of sensor size
Assume: (for toy-tracker)
13 layer tracker with radii = 10 – 130 cm
simple barrel – forward geometry , break at h=  layer area = const x r2
Sensor capacity with fixed pitch variable length Csens = 0.1 pF  3pF
Csens = const x length pixel  strixel  strips
Density of channels  N (r) ~ r2/Csens
Analog power depends on sensor capacitance  Iana = Io + slope x Csens (prev. page)
Digital power dependence on data traffic & particle fluence:
CMSPIX measured  Idig = 32mA mA x fluence-rate [MHz/cm2]

17. 13 Layer Toy SLHC Pixel tracker r = 10cm – 130cm
Csens S Ilayers
[pF] [Ampere] K
K (*) K
Linear power increase with radius. Constant cabling density
per layer
Csensor
[0.1pF]
Layer radius [x10cm]

18. Proposal for low power ohmic link (2006)
together with Optical Information Hubs
Optical links can have very large bandwidth  data hubs
Excellent for long distant (20-100m) information transfer.
e.g. 3.3Gbit/sec link with 1200mW/channel  360 pJ/bit
Optical cabling inside tracker region very painfull, due to variable length. (slack management)
Data transfer inside sensitive tracker region has problem with:
Variable cable length typ. 10cm – 90cm
Individual tracking modules have modest information transfer (~0.3Gbits/sec)
Need for 2 wire ohmic bidirectional link with very low power
Idiff = 0.2mA Z0 = 100 W e.g MHz  12 pJ/bit
Low Current Differential Signal LCDS voltage swing  20mV

19. CMS Pixel Detector BPIX
barrel pixel detector BPIX
forward pixel detector FPIX
Supply Tube (-Z) 5m
Supply Tube (+Z)

20. Barrel Pixel Detector Cabling

21. Barrel Pixel Detector Cabling
BPIX supply tube with electro optical converter
DOH & AOH
modules (66 x 20 mm)
sensor with 16 read out chips (ROC)
and one token bit manager (TBM)
barrel pixel detector

22. Electrical Low Power Data Link
1216 Up links from module to outside the tracking area
320 MBit/s over 1 m
Unshielded micro twisted pair cable (125 µm wire diameter, low mass)
Low power differential driver and receiver (LCDS)
Bundled with power and control wires to one module cable

23. Results, Eye Pattern Wire length: 1 m 320 Mbit/s
40 mV
20 mV
3.125 ns
1m wire
Wire length: 1 m
320 Mbit/s
Minimal amplitude: 20 mV (+/- 10mV)
+/- 500 mV DC offset between driver and receiver
Bit error rate < 10e-12 (different condition)
Crosstalk: -27 dB
Power consumption / link: 4mW (12 pJ/bit)
1.6m wire
2m wire
Measurement done by Marco Rossini, ETH

24. Overview of 4 Layer BPIX System
Insertion checks in CAD and mock-up

25. New Ultra Light Mechanics
CO2 cooling circuit (50mm wall thickness tubes) pressure tested to 100 bar

26. Details of Ultra Light Mechanics

27. Present BPIX System Inner shield ri = 37.3mm
Central beam pipe section has:
cylindrical Beryllium pipe
length = +/- 180cm
rinner=29mm , twall = 800mm
Layer Radius mm mm mm
Tolerance budget during insertion is critical issue
Inner shield
ri = 37.3mm
Clearance in end-position ~ 7.5mm

28. Tracker Upgrade Week, 27.April, 2010
Weight of 2008 Pixel System
DOH & AOH mother board
+ AOH’s
Power board
h = 2.16
endflange prints
Layer 3 & 1+2 10 20
BPIX supply tube 20 40 60 80
100
Total weight of 2008 BPIX within h<2.16 : 16’894 g ~ 16.9Kg
2 Barrels & 4 Supply Tube Sections & Fluid & Cables
Tracker Upgrade Week, 27.April, 2010

29. BPIX in Installation Cassette
Outer shield (C-fibre + Al-foil)
Inner shield (C-fibre + Al-foil)

30. Supply Tube with Optical Read-Out

31. BPIX Upgrade Baseline (2016)
 1216 modules
(present)
Keep present tolerances need R=25mm pipe

32. Tracker Upgrade Week, 27.April, 2010
Weight of 2016 Phase 1 Pixel System 10 20 40 60 80
100
DOH & AOH boards
start at z=1260mm
 h = 2.59
Foam & C-fibre ribs
[cm]
Plugs Layer 3&4
Plugs Layer 1&2
h = 2.16
Total weight of Layer BPIX within h<2.16 : g ~ 6.5 Kg
2 Barrels & 4 Supply Tube Sections & CO2 & Cables
Ratio (3 Layers 2008 / 4 layers 2016) ~ 2.62
Tracker Upgrade Week, 27.April, 2010

33. New Low Mass Supply Tube
Silvan Streuli, PSI

34. Elements of the Supply Tube

35. Foam & CF Ribs & Facets

36. Prototype Aluminum Endflange
Slots for CO2 cooling
Pipe routing for DC-DC converter cooling and Digital Data Opto Hybrids
DDOH-cooling
Power Cables
Total weight incl. screws = 421g

37. New BPIX Supply Tube
CO2 cooling loops are to be inserted

38. Material of New Supply Tube
Missing: CO2-cooling loops, DC-DC-converters, DDOH-boards, fibres, Plugs

39. Present Supply Tube Sector C
Material Breakdown of Sector C
Present Supply Tube Sector C
= 2327g

40. Volumes for BPIX Simulation
define simple volumes for simulation  feasable to be put in for TP
comparison has little Z-dependence, Elements C, Si, Al, (F) dominate 10 20 40 60 80
100
BPIX supply tube
h = 2.16
Outer shield
Sector C Supply Tube
Layer 3
Layer 2
Layer 1
Inner shield
Calculation of volume weights for 2008 BPIX by W. Bertl, S. Worm & R. H
 agrees with Pixel Material Budget NIM Paper .!

41. Volumes of 2008 BPIX System h = 2.1610 20 40 60 80
100
h = 2.16
320g
65g
1685g
1211g
736g
9308g
3181g
Sector C Supply Tube
Total Weight (h<2.16) = 16’506g

42. Volumes of 2016 BPIX System h = 2.16 Outer shield Sector C Supply Tube10 20 40 60 80
100
h = 2.16
Outer shield
Layer 3
Layer 2
Layer 1
Sector C Supply Tube
Layer 4
Inner shield
Same calculation of volume weights for 2016 System by W. Bertl, S. Worm & R. H.

43. 2.5% more than estimate in Upgrade Week 27.April 2010
Volumes of 2016 BPIX System
Ratio (2008/2016)
h = 2.16 10 20
320g
(1.0)
2834g
(3.3)
Sector C Supply Tube
1229g
(0.0)
476g
(6.7)
846g
(2.0)
Reduces multiple scattering term for impact parameter with FPIX !
539g
(2.3)
309g
(2.4)
65g
(1.0) 20 40 60 80
100
2.5% more than estimate in Upgrade Week 27.April 2010
Total Weight (h<2.16) = 6’618g
Ratio (2008/2016) = 2.49
320g +65g shield is too much
 possible to reduce 2x