1. DIRECTOR OF MGM’s COE,NANDED
SR FLIP FLOP USING NAND GATE
Sakshi Bharade, Vaishnavi Bhoskar
MGM’s College of Engineering, Nanded
Abstract :
The RS Flip Flop is considered as one of the most basic sequential logic circuits. The Flip Flop is a one-bit memory bi-stable device. It has two inputs, one is called “SET” which will set the device (output = 1) and is labeled S and another is known as “RESET” which will reset the device (output = 0) labeled as R. The RS stands for SET/RESET.
The flip-flop is reset back to its original state with the help of RESET input and the output is Q that will be either at logic level “1” or logic”0”. It depends upon the set/reset condition of the flip-flop. Flip flop word means that it can be “FLIPPED” into one logic state or “FLOPPED” back into another.
Working:
Case 1:
When both the SET and RESET inputs are high, then the output remains in previous state i.e. it holds the previous data.
Case 2:
When SET input is HIGH and RESET input is LOW, then the flip flop will be in RESET state. Because the low input of NAND gate with R input drives the other NAND gate with 1, as its output is 1. So both the inputs of the NAND gate with S input are 1. This will cause the output of the flip – flop to settle in RESET state.
RS flip flop using NAND gate
Fig.1 SR Flip Flop Using NAND Gate
Case 3:
When SET input is LOW and RESET input is HIGH, then the flip flop will be in SET state. Because the low input of NAND gate with S input drives the other NAND gate with 1, as its output is 1. So both the inputs of the NAND gate with R input are 1. This will cause the output of the flip – flop to settle in SET state.
Case 4:
When both the SET and RESET inputs are low, then the flip flop will be in undefined state. Because the low inputs of S and R, violates the rule of flip – flop that the outputs should compliment to each other. So the flip flop is in undefined state (or forbidden state).
The table below summarizes above explained working of SR Flip Flop designed with the help of a NAND gates (or forbidden state).
Table.1 Truth Table of SR Flip Flop
Result:
As R=S=0, Q=?(Forbidden state).
As R=S=1, Q=previous state.
As S=1, R=0 then Q=0(Reset).
As S=0,R=1 then Q=1(Set).
Conclusion:
In SR flip flop, when S=R=0 then Q=Q’=1. Here Q and Q’ are not complement of each other, which violets basic requirement of latch. This condition is known as race condition or forbidden which is not allowed in SR flip flop.
References:
Anand Kumar, “Fundamental of digital circuits” 1st edition, PHI publication, 2001.
U.A.Bakshi, A.P.Godse, “Digital Electronics” Technical Publications, 2009.
Introduction:
The SR flip-flop is one of the fundamental parts of the sequential circuit logic. SR flip –flop is a memory device and a binary data of 1–bit can be stored in it. SR flip–flop has two stable states in which it can store data in the form of either binary zero or binary one. Like all flip–flops, an SR flip– flop is also an edge sensitive device.
SR flip – flop is one of the most vital components in digital logic and it is also the most basic sequential circuit that is possible. The S and R in SR flip – flop means ‘SET’ and ‘RESET’ respectively. Hence it is also called Set – Reset flip – flop. The symbolic representation of the SR Flip Flop is shown below.
Acknowledgements:
We would like also to thank our guide Mr. A. A. Mane for their inspiration, guidance and support. This constant source of encouragement, support and motivation helped us in a long way throughout the project phase.
Mr. A. A. Mane
MINI PROJECT INCHARGE
Dr. Ms. K. C. Jondhale
PROF & HEAD OF ECT DEPT.
Dr. Mrs. G. S. Lathkar
DIRECTOR OF MGM’s COE,NANDED