1. T3MAPS Firmware
Winter 2014

2. Background
Project start date: September 2013 Initial firmware: December 2013 Design plan: Based off of Brad’s python code to emulate the data generator.

3. Block Design
Host PC
Python
UART
FSM
CLK
UART RX/TX 8
T3MAP
FIFOS

4. FSM Design Four states – Idle, Data, Write, Transmit.
Controls the FIFOS and UART.
100% portable! (With minor modifications for alternative data transfer types.)

5. Software Design Implemented with python.
Currently very basic – only one command supported and no interface.
Used to verify the integrity of the bitstream received from the data_in port.

6. Issues Original firmware design did not work – many, many bugs.
Test benches time consuming to write correctly.
PC to FPGA communication slow and difficult.
Very little help from Berkeley…

7. Current Status Working design that sends 8 bit streams in parallel.
UART can be used up to baud – 24 times faster than current speed encoded in firmware.
Most time is spent opening and closing port..
Software re-write in progress.
Firmware features being added such as state communication to host PC.

8. Future Expansion
With current experience, much less time will be required to implement similar designs in USBPIX or SEABAS.
Most difficult part of either system: Host to FPGA communication.
Large task ahead – rebuilding firmware with command macros taken from Python code