1. A KICK-BACK REDUCED COMPARATOR FOR A 4-6-BIT 3-GS/S FLASH ADC
National Changhua University of Education Graduate Institute of Integrated Circuit Design
A KICK-BACK REDUCED COMPARATOR FOR A 4-6-BIT 3-GS/S FLASH ADC
IN A 90NM CMOS PROCESS
T. SUNDSTROM, A. ALVANDPOUR
IEEE Conference on Mixed Design of Integrated Circuits and Systems, 2007
　Adviser : Shu-Chung Yi
Speaker : Bo-Yuan Shieh
2008/06/16

2. Outline Introduction Differential pair comparator Kick-Back effects
Proposed comparator
ADC implementation
Performance comparison
Conclusions

3. Introduction
Today’s high data-rate communications pushes the development of
low to medium resolution, high speed converters such as flash ADCs
for the front-end.
Kick back is the capacitive coupling of internal signals back to the
input and reference signals as can be seen in figure 1.

4. Differential pair comparator
When the clock is low the comparator
is in equalization mode, disconnecting
the pull-down networks from ground
while equalizing the two output nodes.
The two cross coupled inverters will
then pull the two nodes towards Vdd-Vth.
When the clock goes high the circuit goes
into regenerative mode and current starts
to flow through the pull-down paths.

5. Differential pair comparator
A voltage difference on the inputs will
be translated to a current imbalance causing
one of the output nodes to be discharged
faster than the other. When the two output
nodes approach the trip-point of the two
cross-coupled inverters, the voltage difference
will be amplified to full swing.

6. Differential pair comparator
This comparator architecture is very suitable
for low power applications since large currents
are only drawn from the power supply during
the decision time of the regenerative phase.
This makes the sense-amplifier-based
comparator slower than a track-and-latch type
comparator where the cross-coupled inverter
pair is biased around the trip-point at the start of
the regeneration phase.

7. Kick-Back effects In these types of comparators the high-swing
output nodes are separated from the input
transistors by the inverter pair’s NMOS
transistors. This will reduce the differential
kickback from the comparators back to the
resistance ladder and the input.

8. Kick-Back effects
When the comparator is in equalization phase, the drain and source
nodes of the input transistors, as defined in figure 3, will be charged
towards Vdd-2Vth.
When the comparator goes into the regenerative phase, these
nodes will be discharged through the clocked NMOS transistors.
This quick discharge will cause a common mode kick-back to the
input and the reference.

9. Kick-Back effects
The input transistors will operate in the linear region during the
regenerative phase. Assuming equal tail current and equal drain-
source voltage will lead to the expressions (1) – (4) for the input
transistor currents given in figure 3.
VM=Vcm-Vth-VDS
VΔ is the input and reference difference from common mode
Vkick is the kickback voltage
Voff is the resulting offset voltage

10. Kick-Back effects

11. Kick-Back effects

12. Proposed comparator

13. ADC implementation

14. Performance comparison

15. Conclusions The maximum speed of the proposed comparator was reduced
by 7 % while the power dissipation went down by 16 %.
The kick-back reduced comparators were a key component in
the design of a 4-6-bit, 3-GS/s flash ADC. Lowering the demands
on the input driver and resistance ladder network the overall
power dissipation was reduced by 50% for the same performance.

16. ~ THE END ~
Thank you !