1. Real Time DSP Tools for Laser Microscopy
Hamza Al-Kindi
Tom Carroll
Bassem Faour
Anthony Zilinsky
Introduce ourselves and what specific parts of the project we have been working on

2. Goals
This project aims to create a real time imaging system capable of utilizing the benefits of single photon detection imaging by using two main techniques:
Spatial Frequency Modulated Imaging (SPIFI)
Time-Correlated Single Photon Counting (TCSPC)
[Hamza]

3. TCSPC
Time-correlated single photon counting uses low power lasers to excite a sample enough to release a single photon. The time between the excitation and the photon release is measured and used to classify the sample.
[Bassem]

4. SPIFI
Spatial frequency modulated imaging encodes spatial information in the frequency component of the output signal. This technique should allows scanning of an entire line rather than an individual pixel.
[AJ]Discuss modulation disk: how rotation causes different locations from the center to “flash at different frequency”

5. Prior Work
Prior work focused purely on using an FPGA board for TCSPC. Our initial goal was to use the FPGA board to replicate results from much more expensive TCSPC equipment to make the technique more accessible.
[Bassem, AJ] Explain progress towards prior goals, possibly brief overview of prior techniques.

6. Simulink Model
In order to verify that we were making progress toward a correct output we needed a model that we could compare results to. This would allow us to test verilog code without needing to duplicate tests with another SPIFI setup.
[Bassem]Explain importance of simulink model *get pictures from bassem to include here*

7. Enhanced Analog Front-end
Prior work toward creating a cheaper TCSPC system used the FPGA’s built in LVDS ports and a very simple signal conditioning setup on a breadboard. We aim to adapt a published design to create a more robust and consistent analog front-end for our current design.
Discuss LVDS ports on FPGA board, why they are used instead of A/D converters (cost). Explain origins of current designs.

8. Low Voltage Differential Signaling
Used to compare two signals (V+ and V-)
Logical 1 is outputted when V- is under V+
Logical 0 is outputted when V- is above V+
Discuss LVDS ports on FPGA board, why they are used instead of A/D converters (cost). Explain origins of current designs.

9. Enhanced Analog Front-end
To generate images of our desired sample, PMT signals must be demultiplexed and counted
Using an FPGA allows for a fast enough response time as well as allowing for changes to be made to the hardware easily
FPGA used because of low cost and high bandwidth capabilities
Discuss LVDS ports on FPGA board, why they are used instead of A/D converters (cost). Explain origins of current designs.

10. Enhanced Analog Front-end
PMT signals amplified by coaxial pulse amplifiers
Amplified analog signal sent to dual channel comparator to be transformed into digital signal
Comparator rejects noise and generates a LVTTL (low voltage transistor-transistor logic) signal the FPGA can read in
Discuss LVDS ports on FPGA board, why they are used instead of A/D converters (cost). Explain origins of current designs.

11. Testing with A/D Converter
In order to have a way to test our code and front-end setup independently of the photon counting functionality we aim to use an analog to digital converter as an intermediate design step.
Update with info, where code came from, if/when purchased
Explain why we need for testing
Allows us to test math of verilog code
We have another group test working w lower frequency inputs
Elaborate more in budget

12. Testing with A/D Converter
Will replace the photon counting front-end
Allows us to test math of Verilog code without having the front end up and running
Eliminates need to implement additional Verilog code needed to calculate fluorescence lifetimes of samples
Update with info, where code came from, if/when purchased
Explain why we need for testing
Allows us to test math of verilog code
We have another group test working w lower frequency inputs
Elaborate more in budget

13. Budget Material Cost Remaining Budget Starting Budget $0 $756
[AJ]Discuss tentative purchase of A/D card

14. Current Progress
Much of our progress at this point has focused on gathering information needed to move forward with the project. We now have a substantial code base for testing the photon counting front-end as well as the A/D card. Our Simulink model is providing us with useful results to aim for in our Verilog reconstruction. This progress paves the way for further stages that will require more testing and experimentation.
[AJ]

15. Future Plans At this point, the
next stage of this project is to purchase and begin testing with the A/D card.
This stage of the project will provide us with the first functioning verilog code that will be used in the final, TCSPC version of the project.
Design a lock-in amplifier
Write Verilog code for FFT
Write Verilog code for reading/writing to memory
[Tom] What we hope to present at E-days?
Lockin
FFT-3d-2d
Verilog for R/W to memory

16. Questions? [Tom] What we hope to present at E-days? Lockin FFT-3d-2d
Verilog for R/W to memory