EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 2

EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 2
Ramzan Mat Ayub; SATF 2005 EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 2 Ramzan Mat Ayub School of Microelectronic Engineering

Lecture Objectives Understand the basic operation of MOS Capacitor
Ramzan Mat Ayub; SATF 2005 Lecture Objectives Understand the basic operation of MOS Capacitor Able to calculate the Threshold Voltage for MOS Capacitor and Transistor Understand why isolation is needed in CMOS process Understand the isolation requirements and related design rules Able to describe in terms of wafer cross section, the process steps for Semirecessed LOCOS, Fully Recessed LOCOS, STI and several advanced isolation structures formation.

NWELL PWELL L W POLY A B B’ A’ n+ n+ p+ p+ n+ n+ p+ p+ n+ n+ p+ p+ n+
Ramzan Mat Ayub; SATF 2005 PWELL NWELL A n+ n+ p+ p+ L n+ n+ p+ p+ W n+ n+ p+ p+ n+ n+ p+ p+ B B’ A’ POLY

Device with the same polarity - simpler
Ramzan Mat Ayub; SATF 2005 Device with the same polarity - simpler NMOS NMOS n+ n+ n+ n+ p-well CROSS SECTION ALONG A TO A’ LINE

Device with the different polarity – more complicated
Ramzan Mat Ayub; SATF 2005 Device with the different polarity – more complicated NMOS PMOS n+ n+ p+ p+ p-well n-well n or p-substrate CROSS SECTION ALONG B TO B’ LINE

MOS Device Isolation Requirements
Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Requirements MOS Transistors are isolated as long as; source-substrate and drain-substrate pn junctions are held at reverse bias unwanted channels are prevented from forming among adjacent devices Field transistor DRAIN SOURCE NMOS#1 NMOS#2

Only later they are connected. Improper isolated device will result;
Ramzan Mat Ayub; SATF 2005 Electric circuit in VLSI technology is implemented by connecting isolated devices through specific conducting path. To fabricate monolithic ICs, electrically isolated devices must be created in the silicon substrate. Only later they are connected. Improper isolated device will result; total circuit failure high leakage (large dc power dissipation) noise margin degradation voltage shift, cross talk between transistors and etc. The challenge is VLSI device only allows single transistor leakage < 10 pA/um). On the other hand, process integration imposed a stringent requirement on the isolation technology; spacing between actives should be as small as possible to produce the surface topography as planar as possible isolation process module must be simple to implement and easy to control

Ramzan Mat Ayub; SATF 2005

2 methods of increasing the VTF; making a thicker field oxide
Ramzan Mat Ayub; SATF 2005 VTF is the threshold (minimum) voltage to turn on the parasitic MOS (field transistor) VTF is normally at least 8 V above supply voltage to ensure less than 1 pA/um between isolated MOS device 2 methods of increasing the VTF; making a thicker field oxide Increase the doping beneath field oxide (channel stop implant) Field transistor M-1 DRAIN SOURCE NMOS#1 NMOS#2

MOS Device Isolation Characterization
Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Characterization Test Structures for NMOS Isolation poly poly n+ n+ n+ n+ Aluminum

To find the optimum n+ to n+ spacing
Ramzan Mat Ayub; SATF 2005 The purpose; To find the VTFiso : The gate voltage at which the maximum allowable leakage current arise To find the optimum n+ to n+ spacing Gate voltage (VTFiso) at drain 1nA or 1pA, at VD = Vcc, is measured VTFiso is plotted against n+ to n+ spacing to find the optimum n+ to n+ at certain VDS values

n+ to n+ spacing in micron
Ramzan Mat Ayub; SATF 2005 VTFiso Volts Channel current 25 0.1 u A 20 1 n A 15 10 p A 10 5 n+ to n+ spacing in micron

Overview on CMOS Isolation Techniques
Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Grow and etch thick oxide (1970) Semi recessed LOCOS (1980) Basic LOCOS Poly buffered SILO and etc Fully recessed LOCOS (1980) Side Wall Mask Isolation (SWAMI) Self Aligned Planar Oxidation (SPOT) FUROX (Fully Recessed Oxide) Shallow Trench (STI) (1990) SOI + STI (2000)

Grow and Etch Technique
Ramzan Mat Ayub; SATF 2005 Grow and Etch Technique substrate b) Pattern and etch substrate a) Grow thick oxide c) S/D diffusion

Grow and etch (used until late 70s)
Ramzan Mat Ayub; SATF 2005 Grow and etch (used until late 70s) Thick oxide is grown thermally in the furnace Wafer is patterned and etch Disadvantages Sharp corners, difficult to cover in the latter process steps Channel stop must be implanted before oxide is grown (active to be aligned with channel stop region – low packing density)

LOCOS Isolation Technology
Ramzan Mat Ayub; SATF 2005 LOCOS Isolation Technology oxidation oxidation nitride removal nitride removal a) Semi recessed LOCOS b) Fully recessed LOCOS

Basic Semi-recessed LOCOS Process
Ramzan Mat Ayub; SATF 2005 Basic Semi-recessed LOCOS Process Step-1: Pad Oxide Layer Wafer is cleaned using RCA cleaning technique A SiO2 (called pad or buffer oxide) is thermally grown The function of this oxide is to cushion the transistion of stress between the silicon substrate and the subsequently deposited nitride. Silicon substrate

Step-2: Silicon Nitride Layer
Ramzan Mat Ayub; SATF 2005 Step-2: Silicon Nitride Layer A thick layer of CVD silicon nitride is deposited. The function of this nitride is as mask to the oxidation process. Silicon nitride is very effective as oxidation mask because oxygen and water vapor diffuse very slowly through it, preventing oxidizing species from reaching the silicon surface under the nitride. Silicon nitride however exhibiting a very high tensile stress (1010 dynes/cm2), hence used with minimal thickness. Silicon substrate

Step-3: Photolithography-Active Area Definition
Ramzan Mat Ayub; SATF 2005 Step-3: Photolithography-Active Area Definition To define the active area (where the transistors to be put) Silicon substrate Silicon substrate

To cover the active regions, expose areas to form LOCOS
Ramzan Mat Ayub; SATF 2005 Step-4: Nitride Etch To cover the active regions, expose areas to form LOCOS Silicon substrate

Step-5: Channel stop implant
Ramzan Mat Ayub; SATF 2005 Step-5: Channel stop implant To create a channel stop doping layer under Field Oxide. In NMOS circuit, a p implant (boron, keV) is used, while in PMOS, arsenic is used. PR is removed after the implant Silicon substrate

Step-6: Grow Field Oxide
Ramzan Mat Ayub; SATF 2005 Step-6: Grow Field Oxide Field oxide is thermally grown by wet oxidation at temperatures around 1000C to the thickness ,000A. Oxide will grows where there is no masking nitride, but at the nitride’s edges, some oxidation occurred. This caused the nitride’s edges to lift. Because of the shape, this structure is called bird’s beak. Silicon substrate

Ramzan Mat Ayub; SATF 2005 The bird’s beak is a lateral extension of the field oxide into the active area of the devices. For a typical 8000A LOCOS, bird’s beak ~ 5000A. Limiting factor for the usage of LOCOS. 8000 A FINAL ACTIVE AREA BIRD’S BEAK 5000 A ORIGINAL MASK

SEM picture of Semi-Recessed LOCOS
Ramzan Mat Ayub; SATF 2005 SEM picture of Semi-Recessed LOCOS

Step-7: Strip Masking Nitride Layer
Ramzan Mat Ayub; SATF 2005 Step-7: Strip Masking Nitride Layer Oxynitride etch ( A top layer of nitride) – deglaze process Wet hot phosphoric process to remove nitride (good selectivity to oxide) Tricky process, deglaze process must be carefully characterized. Silicon substrate

Step-8: Regrow and strip sacrificial oxide
Ramzan Mat Ayub; SATF 2005 Step-8: Regrow and strip sacrificial oxide Kooi et al discovered that a thin layer of silicon nitride can form on the silicon surface (pad oxide – silicon interface). This nitride spot is called white ribbon or Kooi Effect and must be removed to prevent defect from occuring when growing gate oxide. This can be done by regrowing a pad oxide and subsequently removed.

Factors Affecting Bird’s Beak Length and Shape
Ramzan Mat Ayub; SATF 2005 Factors Affecting Bird’s Beak Length and Shape Pad oxide thickness Lateral oxidation can be reduced by using a thinner pad oxide, leading to a shorter bird’s beak. Pad layer composition – CVD oxynitride Silicon crystal orientation – shorter bird’s beak in <111> compared to <100> Field oxide process temperature – Shorter with higher oxidation temperature. Thickness and mechanical properties of nitride layer – the thicker the nitride, the shorter the bird’s beak 6) Mask stack geometry – depends on the shape and size of the structures

Advanced Semi-Recessed LOCOS Process
Ramzan Mat Ayub; SATF 2005 Advanced Semi-Recessed LOCOS Process A) Poly Buffered LOCOS Based on the fact that a thinner pad oxide will produce a shorter bird’s beak. Usual pad oxide is replaced with a polybuffered layer; poly 500A:oxide 100A Thicker nitride is used to suppress the bird’s beak more, 1000 – 2500A Q7, Tutorial 1 B) Sealed Interface LOCOS Reduce the bird’s beak by depositing nitride layer directly onto the silicon. Lateral diffusion of oxidants is suppressed better, resulting a shorter bird’s beak. Q8, Tutorial 1

Basic Fully-recessed LOCOS Process
Ramzan Mat Ayub; SATF 2005 Basic Fully-recessed LOCOS Process Step-1: Pad Oxide Layer Wafer is cleaned using RCA cleaning technique A SiO2 (called pad or buffer oxide) is thermally grown The function of this oxide is to cushion the transistion of stress between the silicon substrate and the subsequently deposited nitride. Silicon substrate

Step-2: Silicon Nitride Layer
Ramzan Mat Ayub; SATF 2005 Step-2: Silicon Nitride Layer A thick layer of CVD silicon nitride is deposited. The function of this nitride is as mask to the oxidation process. Silicon nitride is very effective as oxidation mask because oxygen and water vapor diffuse very slowly through it, preventing oxidizing species from reaching the silicon surface under the nitride. Silicon nitride however exhibiting a very high tensile stress (1010 dynes/cm2), hence used with minimal thickness. Silicon substrate

Step-3: Photolithography-Active Area Definition
Ramzan Mat Ayub; SATF 2005 Step-3: Photolithography-Active Area Definition To define the active area (where the transistors to be put) Silicon substrate Silicon substrate

Step-4: Nitride Etch, Oxide Etch, Silicon Etch
Ramzan Mat Ayub; SATF 2005 Step-4: Nitride Etch, Oxide Etch, Silicon Etch To cover the active regions, expose areas to form LOCOS Silicon substrate

Step-5: Channel stop implant
Ramzan Mat Ayub; SATF 2005 Step-5: Channel stop implant To create a channel stop doping layer under Field Oxide. In NMOS circuit, a p implant (boron, keV) is used, while in PMOS, arsenic is used. PR is removed after the implant Silicon substrate

Step-6: Grow Field Oxide
Ramzan Mat Ayub; SATF 2005 Step-6: Grow Field Oxide Field oxide is thermally grown by wet oxidation at temperatures around 1000C to the thickness ,000A. Oxide will grows where there is no masking nitride, but at the nitride’s edges, some oxidation occurred. This caused the nitride’s edges to lift. Because of the shape, this structure is called bird’s beak. BIRD’S HEAD BIRD’S BEAK

SEM picture of Fully-Recessed LOCOS
Ramzan Mat Ayub; SATF 2005 SEM picture of Fully-Recessed LOCOS

Step-7: Strip Masking Nitride Layer
Ramzan Mat Ayub; SATF 2005 Step-7: Strip Masking Nitride Layer Oxynitride etch ( A top layer of nitride) – deglaze process Wet hot phosphoric process to remove nitride (good selectivity to oxide) Tricky process, deglaze process must be carefully characterized. Step-8: Regrow and strip sacrificial oxide Kooi et al discovered that a thin layer of silicon nitride can form on the silicon surface (pad oxide – silicon interface). This nitride spot is called white ribbon or Kooi Effect and must be removed to prevent defect from occuring when growing gate oxide. This can be done by regrowing a pad oxide and subsequently removed.

Advanced Fully-Recessed LOCOS Process
Ramzan Mat Ayub; SATF 2005 Advanced Fully-Recessed LOCOS Process Side Wall Masked Isolation (SWAMI) Bird’s beak free structure, very planar process Silicon substrate Pad Oxidation CVD Nitride Deposition

Sloping sidewall, help to reduce the stress during oxidation
Ramzan Mat Ayub; SATF 2005 Sloping sidewall, help to reduce the stress during oxidation Oxide / Nitride Etch Silicon Etch

Second layer of pad oxide and nitride CVD Oxide
Ramzan Mat Ayub; SATF 2005 Second layer of pad oxide and nitride CVD Oxide

Etch Oxide, Etch Nitride Field Oxidation Nitride / Oxide strip Active
Ramzan Mat Ayub; SATF 2005 LOCOS Etch Oxide, Etch Nitride Field Oxidation Nitride / Oxide strip Active

B) Self Aligned Planar Oxidation Technology (SPOT)
Ramzan Mat Ayub; SATF 2005 B) Self Aligned Planar Oxidation Technology (SPOT) Another modified fully-recessed LOCOS to eliminate the bird’s beak and head. Conventional semi-recessed LOCOS is grown using high pressure oxidation. The LOCOS then removed using BOE SiO2

Nitride and oxide then anisotropically etched.
Ramzan Mat Ayub; SATF 2005 Second pad oxide is grown, followed by deposition of a second CVD nitride Nitride and oxide then anisotropically etched. Second LOCOS is then grown using High Pressure Oxidation LOCOS

C) Fully Recessed Oxide (FUROX) D) OSELO E) ETC
Ramzan Mat Ayub; SATF 2005 C) Fully Recessed Oxide (FUROX) D) OSELO E) ETC

Trench Isolation Technology
Ramzan Mat Ayub; SATF 2005 Trench Isolation Technology 4 major applications Locos replacement for isolation within the well (STI) Isolation in bipolar (Moderate Trench) Latch prevention in CMOS (Moderate Trench) Trench capacitor in DRAM (Deep Trench) 3 categories Shallow trench <1 um Moderate 1-3 um Deep >3um deep Advantages Increase the packing density tremendously Disadvantages Complex to fabricate, very expensive machines Poor uniformity, Low throughput

Oxide polished to surface by CMP
Ramzan Mat Ayub; SATF 2005 Trench etched CVD oxide deposited Oxide polished to surface by CMP

Shallow Trench Isolation (STI)
Ramzan Mat Ayub; SATF 2005 Shallow Trench Isolation (STI)

Silicon On Insulator (SOI) with STI Isolation Technology
Ramzan Mat Ayub; SATF 2005 Silicon On Insulator (SOI) with STI Isolation Technology Completely isolate the transistor on silicon surface from the bulk silicon substrate. Tremendously increase the packing density of IC chip Mainstream isolation technology for high performance ICs for feature size below 0.13um process technology Normally coupled with Copper Interconnect Technology and Low-k Interlevel Dielectric.

EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 2

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