1. CMOS Inverter First Glance

2. The CMOS Inverter: A First Glance
out C L DD

3. CMOS Inverter N Well V DD PMOS 2l Contacts Out In Metal 1 Polysilicon
NMOS
GND

4. Two Inverters
Share power and ground
Abut cells
Connect in Metal

5. CMOS Inverter First-Order DC AnalysisDD V DD Rp
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
Vout
Vin = 0
Vin = 1
Vout Rn

6. CMOS Inverter: Transient ResponseDD DD t
pHL
= f(R on .C L )
= 0.69 R C R p V
out V
out C L C t V
out DD R on C L 1
0.5
0.36 L R n V 5 V 5 V in in DD
(a) Low-to-high
(b) High-to-low

7. CMOS Voltage Transfer Characteristic

8. The CMOS Inverter VTC:

9. PMOS Load Lines S G D D G S V I V = V -V = V +V I = - I V = V -V = V
out I Dn V
= V -V in DD
SGp
= V +V DD
GSp D I
= - I Dn Dp V
= V -V
= V +V D
out DD
SDp DD
DSp G S V
DSp I Dp
GSp
=-2.5
=-1 V
DSp I Dn in =0
=1.5 V
out I Dn in =0
=1.5 V in
= V DD +V
GSp I Dn
= - I Dp V
out
= V DD +V
DSp

10. CMOS Inverter Load Characteristics

11. CMOS Inverter VTC

12. Switching Threshold as a function of Transistor Ratio10 1
0.8
0.9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8 M V
(V) W p /W n

13. Determining VIH and VILOH OL in
out M IL IH
A simplified approach

14. Inverter Gain

15. Gain as a function of VDD

16. Simulated VTC

17. Impact of Process Variations
0.5 1
1.5 2
2.5 V in
(V)
out
Good PMOS
Bad NMOS
Good NMOS
Bad PMOS
Nominal

18. MOS Capacitances Dynamic Behavior

19. MOS Transistor 3-D perspective

20. Dynamic Behavior of MOS Transistor

21. The Gate Capacitance x L Polysilicon gate Top view Gate-bulk overlapd L
Polysilicon gate
Top view
Gate-bulk
overlap
Source n +
Drain W t ox n +
Cross section L
Gate oxide

22. Average Gate Capacitance
Different distributions of gate capacitance for varying
operating conditions
Most important regions in digital design: saturation and cut-off

23. Gate Capacitance Capacitance as a function of VGS
(with VDS = 0)
Capacitance as a function of the degree of saturation

24. Measuring the Gate Cap by Simulation_ 16 X 10 10 9 V GS 8 I 7 6
Gate Capacitance (F) 5 4
Gate Capacitance (F) 3 2 -2
-1.5 -1
-0.5
0.5 1
1.5 2 V
(V) GS

25. Diffusion Capacitance
Channel-stop implant N 1 A
Side wall
Source W N D
Bottom x
Side wall j
Channel L S
Substrate N A

26. Junction Capacitance

27. Linearizing the Junction Capacitance
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest

28. Cpacitive Device Model

29. Capacitances in 0.25 mm CMOS process

30. Computing the Capacitances

31. CMOS Inverters V DD PMOS 1.2 m m =2l Out In Metal1 Polysilicon NMOS
GND

32. The Miller Effect

33. Computing the Capacitances

34. Propagation Delay

35. CMOS Inverter Propagation Delay Approach 1

36. CMOS Inverter Propagation Delay Approach 2

37. Transient Response ?
tp = 0.69 CL (Reqn+Reqp)/2
tpLH
tpHL

38. Design for Performance
Keep capacitances small
Increase transistor sizes
watch out for self-loading!
Increase VDD (????)

39. Delay as a function of VDD

40. Device Sizing (for fixed load) Self-loading effect:
Intrinsic capacitances
dominate

41. NMOS/PMOS ratio
tpLH
tpHL tp
b = Wp/Wn = 1.9

42. Impact of Rise Time on Delay